Characterization of IC Chip Package IBIS Model and Signal Integrity
This one-hour webinar presents an insight into the PCB Signal Integrity simulation and IBIS model characterization process. A review of what exactly signal integrity simulation does on the PCB and at the system level. A discussion on how the IBIS model is a default for analyzing IC Chips’ input/output waveform integrity. The IBIS model is broken down for easier understanding of its operation and integration into the SI simulation. In addition, a quick note on how to achieve accurate results for Signal Integrity simulation.
Speakers Bio:
Cheah Soo Lan has worked on Signal Integrity simulation since the mid-1990s as a research and development engineer for the National Supercomputing Center and high-speed PCB design for the Advanced Electronics Laboratory in the defense sector and the Institute of Microelectronics in Singapore. Cheah is familiar with various types of advanced test equipment, software simulation, and modeling techniques associated with the R&D job scope.
Cheah is currently working as an MIT for IPC CID/CID+ Asia and continues to support the Global Electronics Association with online PCB Design I and PCB Design II courses as well as her upcoming Technical Overview of the Semiconductor Chip Industry course starting August 18th.