In advanced printed circuit board and IC substrate production, the metallization for blind vias and through vias (also called through holes – TH) is essential for the build-up of the PCB or IC Substrate. Filling of vias is important for planarity of the PCB as next mounted layers or components need to be placed with tight tolerance. It also helps to prevent moisture ingress, which can lead to corrosion and electrical issues over time. Filling of through vias with metallic copper by electrolytic plating provides various advantages compared to plugging paste, such as higher electrical and thermal conductivity as well as higher reliability, better mechanical stability, and reduced number of process steps. First through via filling process was described in 2005 [1], but also other emerging technologies, like the replacement of organic materials with glass for the core layer of IC Substrates, would benefit from advanced through via filling processes. Today, through via filling is primarily done in two different types of equipment, namely copper plater with horizontal transportation of the panel and vertical conveyorized plating (VCP) equipment.
Challenges that the industry is facing are driven by PCB and IC Substrate designs that require void-free filling of high aspect ratio [2] structures coupled with overall increasing number of through vias on a panel with areas of high hole density and areas with low hole density. In addition, based on circuitry density, pattern plating might be required.
In order to fulfill the demanding industry requirements, it is important to understand the interplay of chemical (electrolyte) and physical (equipment, process) parameters by identifying key factors influencing the mechanism of the through via filling process. In this paper we will review current state of the art of through via filling with electrolytic copper deposition from established horizontal plating systems [3] to newly developed pattern through via filling in VCP equipment with pulse plating. One example for a filled through via in pattern mode is shown in Figure 1.

In HDI (high density interconnect) PCB (printed circuit board) and IC Substrate (integrated circuit substrate), a successfully formed and plated laser via is crucial to the overall system and/or package functionality, as well as for the product’s reliability. Simultaneously, total via density per unit is increasing, driven by demands for higher feature quantities and enabled through new miniaturization technology in board (substrate and PCB) manufacturing processes and equipment. Hence, the importance of an optimized via formation process takes center stage for the current and next waves of technology development.
Thus far, a board manufacturer’s key process support for via formation has largely come from singular supply chain partners; e.g. via drilling support from one supplier, desmear support from another, plating support perhaps from yet another. While top board manufacturers demonstrate skillful expertise in the total process landscape, new challenges require specific technological development from such key suppliers. And yet, cooperation between process equipment and chemistry suppliers remains punctuated at best, for various reasons, which may limit absolute leverage for true solution finding.
A comprehensive, total via formation process landscape ownership would carry with it many benefits that would otherwise remain unexplored. We’ll focus on what such a single-source via formation development could look like, while simultaneously looking at some new system technology. A holistic via formation approach (pretreatment, via drilling, desmear, electroless/galvanic plating) may support the optimization the interconnect and new advances in form, function and reliability.

Flip chip ball grid array (FCBGA) package substrate components provide the critical building blocks for electronic devices and high-performance computers. They will enable the future of supercomputing, artificial intelligence processing, autonomous cars, and complex semiconductor modules. Maximizing throughput and quality when drilling vias on materials and applications used to produce these components, within a high-volume manufacturing process, has become challenging with current and future specifications.
Current generation laser via drilling systems are capable, but not productive enough for the increasing throughput needs of the top substrate suppliers. Therefore, a laser via drilling system that can deliver both constant power and high via quality on 30-60 μm vias would help enable and transform new technologies at an accelerated rate. Using a quasi-continuous wave laser (QCW) source enables constant laser power to the work surface, which eliminates the wait time needed for pulse availability on traditional CO2 lasers. Via drilling is no longer restricted to stage or galvanometer move-time limitations.
The combination of a QCW laser, acousto-optic device (AOD) beam-steering and modulation technology will enable a new level of throughput and accuracy for ABF drilling. In this paper, we will investigate the principals and deliverables of this emerging technology (Via Drilling System designed for ABF Materials), and how to harness and manipulate the properties of a QCW laser for maximum efficiency. Laser via formation is a foundational step in the integrated circuit and substrate architecture, and a creative combination of laser and optics can further transform the current processes and alleviate production bottlenecks.

The need for cleaning circuit card assemblies is well understood for achieving optimum reliability; contamination present on assemblies can lead to detrimental effects, including dendritic growth and corrosion, inevitably culminating in system failures. The push towards miniaturization and high-density designs utilizing low-standoff components has introduced challenges in achieving complete residue removal. Despite the development of precision-engineered solvents, designed with attributes like low surface tension to remove entrapped residues from small spaces, certain types of packages continue to present challenges within today’s manufacturing environment. Notably, vented components, characterized by small openings that prevent pressure accumulation during reflow, prove to be difficult to clean effectively. These openings tend to entrap solvents and residues, impeding effective removal to guarantee reliability.
In this work, we investigate potential solutions to guarantee acceptable cleanliness of vented components. We consider the propensity of ingress of various solvents and contaminants, the ability of current state-of-the-art solvents to effectively remove contamination trapped within the component and look at methods to efficiently prevent access of the cleaning solvent to the inside of the component. The objective is to provide a comprehensive discussion empowering engineers with vital insights to make informed decisions regarding the cleaning processes of vented components and ensure enhanced reliability and operational longevity of electronic systems.

Direct Digital Manufacturing (DDM) is a growing field in which Additively Manufactured Electronics (AMEs) are manufactured on a single machine through a variety of additive and subtractive techniques. The maturation of this technology has seen increasingly ruggedized, conformal, multilayer circuit structures that have received interest from defense and aerospace sectors. While AMEs have been successfully applied in rugged terrestrial applications, the technology is ready to advance into an even more severe environment. Presented in this work are DDM advancements to enable the additive manufacture of low-earth orbit (LEO) small satellites.
LEO conditions and general satellite operation require new manufacturing and design methodologies in DDM. Mechanical development towards novel Fused Deposition Modeling (FDM) techniques ensured the printed satellite structure could survive LEO temperature ranges and launch stresses. Resulting structures are strong while maintaining dense electrical and thermal functionality. Higher voltages, long range communication, and the need for efficient power handling drove development of new conductive deposition and component securement methods. Resulting circuitry saw increased density, efficient operation, and feature numbers that far exceed typical additive electronics. The additively manufactured nature of the satellite requires a unique and flexible satellite design which blends printed electronics with commercial-off-the-shelf (COTS) devices. These developments have culminated in a modular small satellite system, in which electrical functions are embedded within the printed structure of the satellite, and can be manufactured on a single DDM system. The volumetric savings and manufacturing agility of this satellite highlight the powerful application of DDM for electrically functional structures.

Thorough cleaning processes are necessary due to their critical role in ensuring optimal system performance. Residual contaminants can significantly compromise printed circuit card assemblies' reliability and operational life. Specifically, contaminants soluble in water and possessing ionic properties can exacerbate issues when exposed to moisture, causing undesirable dendritic growth, corrosion, and, ultimately, system failure.
Advancements in board designs have increased heat generation within electronic systems, necessitating more efficient cooling methods. Immersion coolants are highly effective agents for dissipating the generated heat, and most immersion coolants exhibit limited or no miscibility with water and possess limited capability to dissolve various forms of ionic contaminants. This characteristic has sparked discussions on whether traditional cleaning processes are warranted for systems utilizing immersion-cooling mechanisms.
To address this question, test vehicles were subjected to surface insulation resistance testing while immersed in commercially available immersion-cooling fluids to evaluate long-term reliability. Critical parameters such as the level of cleanliness, exposure to moisture pre-immersion, type of coolant, and the type of flux are systematically analyzed and discussed. The goal is to understand how these variables could potentially influence the reliability of products in the context of immersion-cooled assemblies, providing insights to address whether traditional cleaning processes are still needed.

Additive Manufacturing (AM) offers numerous benefits over traditional manufacturing methods, such as realization of unique form factors, decreased waste in material, decreased cost and lead time of tools, and the ability to create rapid prototypes. It is for these reasons that there has been a significant increase in its use in different technical applications, including electronic packaging. In previous studies, AM techniques have been used to create Poly-Ether-Ether-Ketone (PEEK) Near Chip-Scale Interposers (NCSIs) into BGA PCBs manufactured via traditional methods. The conformal vertical interconnects were made using Aerosol Jet Printing (AJP) in five-axis configurations, and the interconnects that connected the interposer to the BGA leads were printed using syringe-dispense methods. This work expands on the prior research by using the optimized parameters and design of experiments to implement AM interposers into a dual-channel, X-band MMIC assembly.

At millimeter-wave frequencies, considerations of electrical performance and PCB durability may often lead to contradictory requirements with respect to copper foil materials and chemical pre-bond treatments. For example, decreased surface roughness will typically decrease conductor loss but may compromise PCB durability. These issues are being investigated by the iNEMI consortium performing a rigorous study, based on copper foils from different manufacturers, where surface roughness and loss properties of the foils are independently evaluated. An original contribution from the authors of this paper resides in providing easy-to-use instruments, based on mmWave resonator heads, for measuring the effective conductivity of copper foil samples. Such techniques alleviate the need for manufacturing a test vehicle (such as a strip-line segment) and naturally deliver the loss due to the copper, separated from any substrate losses, as no substrate is involved in the measurement.
This paper and conference talk will explain the physical fundamentals of the developed methods, illustrated with the results of copper foil measurements in the 13- 40 GHz range.
We shall focus on Sapphire Dielectric Resonators (SaDR) and plano-concave Fabry-Perot Open Resonator (pc-FPOR), developed with the use of full-wave electromagnetic modeling. Conformal FDTD method is applied for both instrument design and physical insights into the measurement process. Extensions to higher frequencies are underway and will be signaled.
The presented testing methods will help copper foil manufacturers improve manufactured products quality and accelerate new product development. New and better foils will contribute to advancements in PCB manufacturing and overall 5G technologies.

As the electronics industry continually strives for innovation and efficiency in assembly and rework processes, the exploration of low temperature (LT) solder alloys has gained significant attention. This paper provides a comprehensive analysis of LT solder, particularly focusing on its application in rework processes and the broader implications for electronics manufacturing. We delve into various facets of LT solder, examining both the potential benefits and the challenges associated with its use.
The study revisits previous work on LT solder in rework, offering a detailed summary and suggesting a cautious approach due to the increased costs and complexities associated with bismuth-containing solder wire, alongside a lack of substantial differences in joint strength and reliability compared to traditional methods. Additionally, the paper addresses broader considerations of LT solder, including benefits and drawbacks, performance tradeoffs, and areas for further study.
This investigation into LT solder is further enriched by new data on the cleaning of bismuth oxide residues and the effects of tip temperature and contact time on IMC formation during rework. By providing a thorough overview of existing research and new findings, this paper aims to offer valuable insights to manufacturers, engineers, and researchers, contributing to informed decisions regarding the adoption and integration of LT solder in electronics rework and assembly.

The global interest in reducing CO2, as demonstrated by carbon neutrality, is growing in order to achieve a low-carbon society. Electronic packaging industry is seeing the importance of SnBi-based low-temperature solder (LTS) as it can reduce CO2 emissions during the assembly process.
While the soldering temperature of conventional SnAgCu solder is approximately 250℃, the temperature of SnBi-based low-temperature solder is approximately 170℃, enabling processing temperatures as low as 80℃. Despite the possibility of low-temperature assembly, SnBi-based low-temperature solder poses specific challenges and its use in the market has been limited.
The issues with SnBi-based low-temperature solder include the reliability of solder joints and the non-coalescence of BGA balls and solder paste known as HiP (Head-in-Pillow). Furthermore, in recent years, there has been an increased focus on electrical reliability, including electromigration, which is not exclusive to SnBi-based low-temperature solder.
This study presents the research results on the aforementioned phenomena from the perspective of SnBi-based low-temperature solder.