As the data rate is getting faster with the development of applications such as High Performance Computing (HPC), Data Center, and Artificial Intelligence (AI), it is found via stubs are affecting the signal quality on those server Printed Circuit Boards (PCBs). The back drill process has been adopted to mitigate the via stub effect, but there can be skewed drilling which causes via stub residue in manufacturing of the PCBs. Therefore, using a impedance measurement technique by time domain reflectometry (TDR) to confirm the quality of via back drilling may be necessary. However, the resolution of the TDR instrument for via stub inspection is affected by the quality of channel and accessories. How to ensure the quality of the system before measurement is very important. Three approaches were proposed to achieve the robust and accurate measurement process. In the beginning of the experiment, a transmission line with via stub effect was designed as the device under test (DUT). It was sent to the Taiwan Accreditation Foundation (TAF) testing laboratory to obtain a reference value. The reference value includes minimum via impedance and main routing impedance. The next step is to use one-way analysis of variance (ANOVA), to investigate the impact of different contact impedance and probe skew on via impedance and main routing impedance. In the final step, linear regression is used to evaluate probe quality assurance for the robust and accurate measurement, which means probes with less effect to via impedance. Linear regression method is used to evaluate the impact rate for probes quality selection. If the impact rate is less than 5 %, the contact impedance and skew of probe characterization is less than 4.5 ohms and 45ps, respectively. Another characterization approach is the use of vector network analyzer (VNA) for TDR impedance measurements. A VNA with a higher frequency has a faster rise time and a better resolution length. In addition, VNA also has correction technology to mitigate the error of the system path, such as RF cable and probe.

Solder voids affect the thermal and electrical properties of solder joints, reducing their reliability. The main test for solder voids is non-destructive testing using X-ray transmission images. However, since X-ray images contain noise, it is difficult to automatically extract voids through image processing such as thresholding, and the inspection automation has not progressed. Additionally, IPC-J-STD-001HA/IPC-A-610HA defines quality standards for solder coverage, which should be able to be automatically inspected for various types of components and solder joint types. Therefore, in this study, we verified the methods for automatically measuring solder void ratio and solder coverage using multi-class segmentation technology using deep neural networks. We created a unique dataset of 1,200 X-ray images covering the components and mounting types in the IPC standards, and we thoroughly evaluated the performance of the methods. By training DeepLabv3++ on the 960 training images, it achieved 0.9752 of IoU and 0.9874 of Fscore for the 120 test images. This method was superior to the methods using thresholding processing and the other methods using deep neural networks. Furthermore, it was found that the solder coverage automatically measured using this method had a maximum error of only about 3% compared to the manually measured results. These results suggest that it is possible to accurately and automatically check whether the solder coverage of various components and mounting types meets the IPC standards not only by sampling inspection but also by in-line inspection.

Solder resist (SR) is applied to the outermost layer of printed circuit boards (PCBs) for surface protection and electrical insulation. It is crucial for the reliability of PCBs to ensure robust adhesion between SR and Cu. Current PCB manufacturing employs techniques that chemically induce micro-controlled roughness on the Cu surface, considering factors such as the surface roughness of Cu, the resin content of SR, and the type of filler. Even though heat exposure is known to deteriorate SR/Cu adhesion, the response of the SR and Cu interface to thermal aging remains elusive. In this study, a series of quantitative measurements and morphological analyses were performed to reveal how thermal aging affects the interface between SR and Cu. The growth of Cu oxide during thermal aging leads to the development of a gap between the Cu and Cu oxide layers, making the SR/Cu interfaces vulnerable to delamination. The gap formation between Cu and Cu oxide can be attributed to Cu diffusion-induced Kirkendall voids, as well as differences in crystal lattice, volume, and coefficient of thermal expansion between Cu and Cu oxide.

Metals have long been used as thermal interface materials (TIMs). Due to their high reliability and thermal conductivity, metal TIMs are excellent solutions for heat dissipation in electronic systems, especially for more challenging applications. Thermal conductivity and interfacial resistance are the most important properties of a TIM. One of the biggest obstacles for using metal TIMs is the interfacial resistance. Most metal TIMs are quite stiff and require compressive force to maintain necessary contact with active components to lower the interfacial resistance. With devices becoming smaller, consuming more power, and producing more heat, finding the right TIM becomes a highly critical step in any electronic systems application. Recently, liquid metal TIMs have gained popularity, especially for thermal management of high-performance computing semiconductor applications such as in CPUs, GPUs and MCMs. Due to their fluid nature, liquid metal TIMs do not need to be compressed to maintain even contact, and they can accommodate imperfections in the neighboring components. The newest metal TIMs are made of liquid metal paste (LMP). These gallium-based, high viscosity materials maintain all the good properties of liquid metals, but also offer some improved mechanical properties. A key challenge is applying LMPs consistently through traditional dispensing techniques, like time-pressure, or advanced techniques, such as jetting technology. Both techniques will be compared based on dispense quality, weight repeatability on substrates, and valve-hardware stability. This paper addresses the challenges faced during LMP dispensing in high-volume manufacturing, and how to control several variables affecting dispensing for higher throughput and process reliability.

There is a global consensus that the environmental impact of electronics needs to be reduced. The first step towards this goal is identifying the environmental hotspots in electronics manufacturing, usage and potential recycling. Quantification of the impact of electronics manufacturing is a prerequisite to this assessment. This study focuses on a vital part in the supply chain of electronics: the production of the printed circuit board (PCB). Available datasets containing energy consumption, water and material usage and waste generation during printed circuit board manufacturing are often static and consider only limited design variations. Due to the lack of better alternatives, these Life Cycle Assessment (LCA) datasets are used as generic drop-in replacements for any type of printed circuit board. This paper presents a design-driven parametric approach to model the energy consumption, water, chemical and material usage and waste generation of PCB manufacturing. This methodology is combined with a simplified method for data collection by the PCB manufacturer. The validity of the model is demonstrated by benchmarking against available LCA datasets as well as through demonstrating the influence of design choices such as layer count, routing density, PCB dimensions and type of surface finish. In addition to LCA practitioners, the model can be used by PCB manufacturers to calculate their energy consumption or water usage for their environmental impact reporting needs. Furthermore, it allows to identify hotspots in the production flow for environmental impact reduction purposes.

Flux which facilitates fine bump development and bump pitch was developed. The purpose was to achieve fine bump and bump pitch by securing rheological properties that are similar to, or an improved version of, mass-produced flux. To achieve the goal, the rheological properties of the flux had to be modified, so that solder paste could easily slip through a metal mask to form a fine pitch The ultimate focus was to develop a flux with an initial viscosity between 200~350 Pas and a thixotropy index (TI) higher than 3.0.. In this study, it was discovered that the realization of fine bumps is facilitated by a fluid with high elasticity, encompassing the crossover point (COP), storage modulus (G'), and loss modulus (G''). It was found that the key factors are the initial viscosity, thixotropy index (TI), and occurrences of COP.
In conclusion, the desired rheological properties were achieved in the composition of sample-09 (SP-09). In combination of SP-09 with initial viscosity 275 Pas, TI higher than 3.0, and COP higher than 100 Pa, it successfully printed using the mask with 26 um metal mask opening (MMO). It was expected that the reduction of bump pitch beyond the limit of current mass production capability and the establishment of strong competitiveness through material dualization would be facilitated by the new flux.

Thermosetting epoxy resin is widely used in electronic materials for its excellent insulation, heat resistance, mechanical properties, chemical resistance and processability. However, the non-metallic part of printed circuit board (PCB) is difficult to be degraded and recycled due to the infusibility and insolubility of the traditional thermosetting epoxy polymer. In this paper, a novel halogen-free degradable copper clad laminate (D-CCL) was developed and processed into degradable PCB (D-PCB). The main properties of D-CCL and the reliability of D-PCB were tested. Then，the non-metallic part of the degradable material was degraded by chemical treatment in the degradation solution, and the feasibility of recycling the degraded recycled mixture in composite epoxy material (CEM) was investigated. The results showed that the main performance of the novel D-CCL could meet the performance requirements of conventional halogen free FR-4. The processability and reliability of D-PCB were comparable to that of the conventional FR-4 counterpart. Both the liquid and solid contents separated from the non-metallic degradation mixture could be recovered and applied to manufacturing of CEM, such as CEM-1.
Key words: Epoxy resin, Degradable, Recycling, CCL, PCB, CEM

2.5D is representative advanced packaging technologies that combine multiple integrated circuit dies into one package using silicon interposer. And 2.1D bridge technology, which inserts high-density circuit components into low-density boards, is also one of the advanced packaging technologies replacing 2.5D packaging. In common, both are based on the semiconductor technology of silicon wafer. PCB substrate makers have accumulated a variety of technologies for fine micro circuit. It is possible to prepare organic interposer replacing silicon interposer. A different approach has been tried to implement a 2.1D package substrate named eHDIL (embedded High Density Interconnection Layer) without silicon wafer and damascene process. Thin 4-layer organic substrate with L/S 2/2 was made by semi-additive process (SAP) on Cu foil with a removable glass carrier called HRDP. The thin substrate was implanted into a package substrate for 55um or less bump pitch chips such as HBM memory or chiplet through very accurate die mounting and via connection. Where the line pitch of the HDIL was 4 um, via diameter was 5 um, and total thickness was 30 um. This study demonstrates that advanced package substrates can be developed with PCB substrate material and technology.

The July 23rd webinar, “Electronic Essentials 101: What You Think You Know – and More,” presented by Greg Merrill, offered a practical refresher on core electronics concepts like voltage, current, resistance, and capacitance. Designed for both new and experienced professionals, the session revisited foundational principles while addressing common misconceptions and overlooked details. Through real-world examples, Greg highlighted how a deeper understanding of basic components can lead to smarter design decisions and fewer troubleshooting headaches. This session was ideal for anyone looking to sharpen their fundamentals and apply them more effectively in their work.

This article is a series of studies on a new generation of CPU socket challenges and component interconnect technology for high-end computer product applications. These products encompass computer server and data storage for cloud computing applications at the Data Center as well as core routers for service providers, edge, and branch routers for enterprise networking companies. All these cloud computing products require high data speed in Gigabytes per second and high signal integrity for the massive mobile users and IoT applications whenever and wherever the user wishes to connect. As the finer 3nm semiconductor process is progressively migrated into mass production in the chip fabrication industry to enhance transistor density, increase speed and lower the power consumption of the chip, there are great technical challenges in component packaging design with the circuit board.
The purpose of the Part 1 study is to look into the next generation of CPU socket design correlation with its interconnection system and PCBA manufacturability. Socket pin configuration related to pin true position and common bent pin issue due to transportation stress and material handling are very critical variables. Socket packaging design especially the cover will be carefully examined to avoid laser light leaking/reflection issue so as to avoid pick and place problems in device placement in the PCBA process. Past experience tells us the contamination at the contact pin interface such as particulate, process material residue and oxidation are very important variables to be controlled to avoid contact resistance issues. Socket material selection and mechanical construction are major contributors to package flatness and correlated warpage between the socket package and PCB.
The purpose of the Part 2 study is to look into the next generation of CPU socket design correlation with its interconnection system and PCBA manufacturability through a technical forum in the iNEMI (International Manufacturing Initiative) 2023 Board Assembly--CPU socket interconnect technology roadmap. A team of experts from CPU suppliers, socket material researchers, ODM companies initiated a review to brainstorm key technology trends for next ten years, to identify the technical needs, gaps, and challenges, and then propose potential solutions for the major technical issues. Over the next decade, there is a projected exponential increase in computer data rate in Gb/s due to the IoT from the massive mobile users in the field for their whenever and wherever needs. In such a trend, the socket pin count will be in exponential growth over time, mainly driven by the increase in total computer power, memory and input/output signaling bandwidth. With this exponential increase in pin count, there is a trend to push the similar increase in LGA socket mechanical loading. This increase in loading affects hardware complexity, costs and socket keep out area on the board which in turn could impact overall computation density per motherboard. The data rate increase overtime is forcing lower height sockets to meet the high speed signaling integrity requirement. This reduction in height can promote more complexity to the LGA pin design to meet mechanical requirements as well as forcing larger warpage in socket which can be an interconnect issue at the LGA and motherboard interface.