The search for novel adhesion promoters (AP) for inner-layer bonding of printed circuit boards that meet the requirements of high-frequency applications is driving the surface treatment industry away from established technologies and toward novel solutions that use chemical compounds as the primary source of adhesion. One reason for this is to avoid negative effects on signal integrity (SI) performance and minimize dimensions of the conductive path caused by etching and roughening the surface material to achieve mechanical adhesion to the substrate material. This change in technology leads to new challenges not only in developing viable adhesion promoters that are compatible with many substrates, but also in establishing appropriate quality control procedures for chemical bond coatings.

This study focuses on the characterization of a novel hybrid adhesion promoter that combines anisotropic nano etching with a chemical adhesion layer based on a self-synthesized silane compound. To determine its functionality, it is compared to established processes using laboratory and production data. Since the thickness of the adhesion promoter, introduced at the interface between the organic polymer and the copper substrate, can significantly affect its functionality, a suitable method for determining its thickness and distribution is reported. This nondestructive thin layer detection method will be discussed, establishing accurate correlation to its thickness measured by standard focused ion beam scanning electron microscope (FIB-SEM) techniques.

An electrical model of a thermally damaged microvia has been constructed incorporating observations from electrical test, Scanning Electron Microscopy (SEM), Transmission Electron Microscopy (TEM), and electron backscatter diffraction (EBSD)(1,2). These observations indicate that the change in the structure during thermal cycling, typically cracking, occurs in the vicinity of an internal interface in the microvia, in the immediate vicinity of the electroless copper deposition. This localized damage region allows construction of the model referencing post-test to pre-test resistance ratios.

The model uses a five percent resistance change as an indicator of significant damage in the interface layer which incorporates only a small amount of the overall copper in the microvia. The sensitivity of the model to initial conditions has been assessed by varying the distribution of copper in the interface and microvia regions.

Observations(1,2) indicate that this resistance increase is usually due to a crack in the interface, and the model confirms that a crack that generates a five percent overall resistance shift would impact approximately ninety percent of the interface area. In cases where no crack is observed, the calculated increase in resistance can be compared to the effect of electron scattering from crystallographic defects, such as vacancies, lattice defects, grain boundaries, and impurities. Finally, there are cases where the microvia has been observed to fail after a period in storage. The analysis considers that these could be caused by completely separated interfaces which maintain an Ohmic contact through either mechanical contact or tunneling.

Open circuit failure in microvias is an important issue for critical device reliability yet remains poorly understood. Separations at the microvia-target pad interface caused by board-normal tensile stress from heating during solder reflow in manufacturing can produce opens that show immediately or present as pernicious opens that manifest at module, sub-system, or system level testing and operation.

The present project involves a series of samples from failed boards, non-failed boards and experimental D-coupons, applying advanced high electron microscope resolution imaging and elemental analysis tools to the microvia-target pad interface regions in cross-sectioned microvias. One of these tools, electron backscatter diffraction (EBSD), has revealed that the interfaces of failed microvias are microstructural discontinuities, with the grain structures of both sides terminating at a relatively flat plane that is oriented in a poor orientation with respect to the primary tensile stress direction and comprises a significant structural weakness with respect to crack/separation formation and propagation resistance and electrical failure.

Transmission electron microscopy (TEM) further reveals nanometer-scale concentrations of apparent contaminants along the interface, probably representing residue from the electroless copper deposition or related manufacturing steps.

Microvias from a lot exhibiting especially mechanically strong interfaces show a unique microstructure in EBSD: “Fan” grains, which are fine, blade-like clusters of radiating grains oriented approximately parallel to the central axis of the microvia and extending from the interior of the target pad into the interior of the microvia. This feature effectively strengthens the interface, eliminating the path of cracking/separation propagation weakness and imparting a stronger microstructure for improved reliability.

The ongoing COVID-19 pandemic has highlighted the importance of remote healthcare for the well-being of society. On-body devices designed to detect vital signals, dispense medications, and perform other functions should be soft and conformable to maximize comfort and effectiveness. Rigid printed circuit board materials like FR4 are too rigid to conform to a human body in action. Even conventional flex circuits materials like polyimide are too stiff for many applications. A soft circuit material based on a novel, high-temperature resistant, non-silicone polymer system was developed and investigated. Films made with this polymer are much softer and more stretchable than polyimide films. The elastic modulus of this film was 14 MPa and elongation ratio at break about 130 % with a temperature resistance of greater than 260 °C. To form single-sided circuits, the liquid resin (varnish) was first coated onto a copper foil, then dried and cured. To form double-sided circuits, a second foil was laminated to the backside after drying. The same polymer system was also used to make a compatible pliable coverlay or solder resist. Soft and pliable circuit boards were manufactured with these materials using conventional PCB manufacturing processes including photolithography, chemical etching, laser drilling and plating. Additionally, fully functional devices were made using typical SMT materials and processes to solder components onto the formed circuit boards. This paper describes the properties of the novel polymer system used to make these unique soft circuit materials as well as processed to form and assemble a functional pliable sensor device.

Heterogeneous integration has become one of the most important approaches in the semiconductor technology world. The process nodes are constantly shrinking from 16nm to 5nm and lower, with CMOS component speeds continuously increasing. This is equivalent to integrating twice the number of components in the same amount of space every 18-24 months.

CoW (Chip on Wafer) is the next generation of CoS (Chip on Substrate) that first combines the chips to the interposer, adds wafer-level molding, and finally, they are connected to the flip chip (FC) substrate. This technology makes a better physical structure for accommodating very large die and larger overall interposer dimensions.

At Apex 2022, a technical paper titled ‘Defluxing of Copper Pillar Bumped Flip Chips’ was presented. This comparative study confirmed that compared to low concentration alkaline cleaning agents, the De-ionized water inline cleaning system is challenged to consistently and effectively clean flux residues underneath low standoff components under copper pillar packages with 150μm pitch and a 30μm Cu pillar height.

This study is the continuation of the initial effort but now focuses on cleaning under the next level of ultra-fine pitch CoW devices down to less than 25μm bump pitch and bump counts more than 150K. The authors followed the test protocol utilizing the same low-concentration alkaline cleaning agent used in the initial study. In addition, the study also focuses on the impact of wash temperatures and conveyor belt speed. T

he cleaning assessment methodologies employed analytical/functional testing, including Visual Inspection, FTIR with color mapping, and SEM/EDX.

The use of modern laser systems for depaneling printed circuit boards can present many advantages as well as some challenges for the production engineer compared to conventional mechanical singulation methods. It is particularly important to properly understand the effects of the laser energy to the substrate material in order to take advantage of the technology without creating unintended side effects. The temperature response of the substrate is of central importance for many factors such as the distance of components from the cutting channel or the degree of carbonization. This paper presents an in-depth analysis of the temperature behavior of FR4 material for different laser powers and wavelengths. The temperature measurement was carried out by using Type-K thermocouples applicated in non-plated through holes. These have been positioned at distances with a regular interval to the cutting channel. Thereby the temperature was measured three times for each distance during the ablation process. The result is information on the heat input in 100 µm steps distance from the cutting contour during the laser ablation process through copper layers and PCB base material. Based on the regular measurements, a temperature behavior model can be derived from the data using statistical methods. This paper is examining if the temperatures of all systems measured are considerably below the melting points of tin/silver/copper alloy, even at the smallest intervals. In addition, the authors are investigating the possible correlation between different laser wavelengths, pulse durations, laser power and cutting strategies and its impact on temperature level measured on the substrate material.

Increasing demands on printed circuit boards require new production methods. For years, lasers were mainly used for application with the highest accuracy requirements. Today, laser depaneling became more widely used since the demand for excellent cutting quality, especially for high-end applications (e.g. 5G, IoT), and increasing cost pressure require one to reevaluate the use of traditional production methods. These days lasers offer only benefits over traditional processes. In this paper, the most important facts about process quality and economic advantages are discussed. This paper analyses latest results of quality assessments and shows how laser cutting enables failure-free processes. Dust free cutting and uncontaminated surrounding PCB surfaces with highest technical cleanliness improves the durability of electronics. In the back-end of SMT lines, modern lasers enable significant cost savings with 100% stable process conditions. Several comparisons with traditional depaneling methods are described to show potential savings in PCB materials as well as cost savings in follow-up costs, post processing and efficient and fast volume scaling of production. With mathematical models about design rules and panel utilization this paper encourages PCB designers to enable economical and environmentally friendly SMT production lines.