The electronic packaging industry is undergoing a revolutionary convergence between the printed circuit board segment and the semiconductor packaging segment. New, streamlined and hybrid package architectures are emerging to meet future product requirements – particularly for mobile electronics and infrastructure to support industry megatrends like 5G. There are new challenges for forming electrical interconnections between different types of package elements while maintaining high volume manufacturability and reliability.
In particular, the use of high speed and high frequency dielectric materials complicates the PCB fabrication process. Generally, these low loss and low Dk materials are not amenable to multiple lamination cycles due to the nature of their chemistry; however, conventional PCB fabrication techniques that circumvent this problem by using plated-through-holes introduce undesirable resonance structures and consume precious real estate that could otherwise be used for routing.
Transient liquid phase sintering (TLPS) paste vias can be used to either augment or replace sequentially formed plated microvia interconnects, which necessitate multiple lamination cycles, as well as plated-through-holes (PTH) with their attendant loss of routing density and lossy stubs. TLPS-filled z-axis interconnect layers can be fabricated in parallel with individual x-y trace layers or PCB subconstructions of multiple layers with PTH, interleaved, and laminated in a single cycle. The circuit layers thus electrically joined through the z-axis can be of the same or different materials, complexity and native construction. The adhesive surrounding the TLPS interconnects and mechanically joining the circuit layers can be prepreg or film adhesive and be selected for its adhesive, dielectric and mechanical characteristics. With an appropriate adhesive layer, the TLPS z-axis interconnect concept is extendable to applications outside of PCB construction including area array assembly and thermal transfer.
TLPS pastes, which metallurgically bond to circuit pads, offer both high performance and versatility of installation that is conducive to high manufacturing volumes. Because sintering pastes can be formulated with a variety of particle sizes and flow behavior this technology can provide a spectrum solution to applications from filled microvias in either a printed circuit board or semiconductor package scale, to printed bumps for interconnection of subassemblies, to thermal interfaces with embedded heat sinks.
This paper will present the two most common implementation flows for the installation of the TLPS paste z-axis interconnects in mixed mode PCB constructions.