High Density Interconnect (HDI) Printed Circuit Boards (PCBs) and assemblies are essential to allow space projects to benefit from the ever-increasing functionality of modern integrated circuits. The European Space Agency (ESA) in collaboration with its industrial partners have been updating their standards for PCB design, qualification, and procurement, which also include advanced PCB technologies such as microvias. Results from a wide range of microvia reliability testing have been obtained, which include modelling, assembly simulation, chamber thermal cycling, current induced cycling, and various other accelerated coupons tests.

In complement to the efforts on design, testing and modelling of various microvia configurations, the manufacturing processes have been reviewed in-depth as a result of weak microvia failures. This has been done in close collaboration with qualified PCB manufacturers and their chemistry suppliers. Corrective actions and various other recommendations have been listed in microvia process guidelines [1]. This can also be used for conducting a process audit with a level of detail that is still appropriate for general engineers without detailed chemical background. This paper presents the content of these microvia process guidelines, with the intention to provide support for the review of these complex processes.

This slide show discusses Automation of IST testing.  It utilizes Dielectric estimation laminate assessment method (DELAM).  The slides utilizes thermo-graphics to locate the failure in microvias.  The microvias are tested using IST standard X design and Reflow cycling.    Different Microvia structures were tested and compared.  This includes stacked and semi stacked microvia structures.  

The push for faster data rates and increased signal density in printed circuit boards (PCBs) increases the risk of signal crosstalk on high-speed communication busses which can be highly detrimental to system performance. Interlayer crosstalk between vertical layers is a significant contributor to eye degradation and overall signal quality. This phenomenon can occur when signal traces are routed above/below plated through hole (PTH, also referenced herein as “vias” or “pins”) antipad on the adjacent reference planes, exposing traces on neighboring signal layers to each other. This interlayer crosstalk can be minimized by reducing manufacturing driven layer-to-layer misregistration and reducing the antipad diameter around back drilled PTHs. However, implementing these improvements in the PCB manufacturing process adds cost and raises potential reliability concerns. For example, reducing the PTH antipad diameter on the planes through which backdrilling will occur increases the probability of copper plane exposure after backdrilling. This could pose a shorting risk due conductive anodic filament growth, electrochemical migration, or copper burrs.

This paper provides a cost-benefit analysis of PCB process improvements to reduce interlayer crosstalk, including a reduction in the allowable misregistration between adjacent cores and reduced antipad diameter around back drilled holes. As a part of this analysis, the signal integrity (SI) improvements gained by reducing core-to-core misregistration from 127 µm (5 mil) down to 76.2 – 101.6 µm (3 - 4 mil) were modeled as well as the SI improvements gained from reducing back drilled hole antipad diameter from 0.76 mm (30 mil) to 0.71 mm (28 mil) or even less for a 0.3 mm (11.8 mil) primary drill. The relative cost adder of these improvements was estimated based on PCB manufacturer input. Further, the reliability of backdrill exposed ground and/or power planes with and without hole fill was evaluated through temperature/humidity/bias testing and micro-sectioning of PCB coupons. It was found that reducing the antipad diameter around back drilled PTHs had more impact on crosstalk reduction than reducing the core-to-core misregistration. Taking signal/power integrity benefits, reliability, and cost into consideration, recommendations for pursing reduced core-to-core misregistration and smaller antipads around backdrilled holes are provided.

Optimal breakout of ultra-fine-pitch ball grid array (BGA) packages requires a mix of via structures – through and blind mechanical, stacked and staggered laser – often implemented in thicker PCBs with higher part densities. PCB fabricators have expanded their process capabilities, making these structures manufacturable in the same board, but mismatches in z-axis expansion within the PCB can lead to solder joint failures during PCB assembly (PCBA). The authors will explain these failures, how they were tracked to use of via-in-pad, plated over (VIPPO), and how new materials can prevent these failures through better matching.

The continued miniaturization of both packaging and component size in next-generation electronics presents a significant challenge for PCB designers and PCB fabricators. To effectively navigate the constraints of the traditional subtractive-etch PCB fabrication processes, PCB designs require advanced PCB fabrication capabilities pushing the limits of finer feature size, higher layer counts, multiple levels of stacked microvias and increased lamination cycles. Semi-Additive PCB processes, which can be implemented and integrated with existing PCB fabrication equipment and processes, provide an alternative that effectively resets the SWaP-C curve while increasing reliability.

The ability to design with and manufacture a 15-micron trace and space repeatedly and reliably provides options and opportunities previously not available to PCB designers and PCB fabricators. While just scratching the surface, SemiAdditive PCB processes can: • reduce the number of layers needed for routing high density BGA’s

• increase the hole size

• reduce the number of microvia layers required

• dramatically reduce size, weight and packaging and conversely increase the electronic content within an existing footprint

These benefits and more are being explored and realized as PCB fabricators implement semi-additive processes into their manufacturing facilities.

This session will begin with an overview of Semi-Additive technology as it relates to PCB fabrication including materials, equipment required, and process flow. This overview will be followed by a discussion of reliability test results and signal integrity modeling and will close with the discussion of use cases demonstrating the various ways the technology can be applied.

The combination of increased I/O density, reduced footprint, and multi-die capability within a single platform makes embedded die an attractive solution. The benefits of embedding active die include miniaturization, improved electrical & thermal performance, heterogeneous integration, and an opportunity for cost reduction. Currently vertical integration is happening in power management chips with embedded components integrated into modules. Heat dissipation in integrated 3D high efficiency power modules is challenging when die is embedded inside the substrate. Heat dissipation affects efficiency and electro-migration of the packaged structures. Circular vias can be replaced by copper bar vias in the substrate design for thermal improvement. The thermal improvement is simulated using Ansys FEM (Finite Element Method) tools.

Key words # Embedded die, Fan Out Wafer Level Module, Thermal Improvement

The reliability control in airborne electronics products is essential due to safety and business reasons. As users do not have confidence in raw results provided by previous reliability prediction methodologies, FIDES has the objective to build up this confidence considering technology, process and use. After more than a decade of RoHS legislation and the beginning of the lead-free transition of airborne electronics, it is imperative to consider an appropriate lead-free process factor (П𝐿𝐹) in the reliability prediction. As shown in this work, aeronautical, military and medical industry have waivers that allow them to continue using lead to ensure reliability. Some industries apply components that have lead-free surface finishes with tin-lead soldering alloys. These mixtures, higher temperatures, different reflow times, and other factors introduce risks to the product reliability mainly when subjected to thermomechanical fatigue during long life cycle.

This work presents a new approach for the lead-free process factor (П𝐿𝐹) and new recommendations for the lead-free grade (LF_grade). An analysis was performed of the current recommendations for lead-free grade (LF_grade). Thirteen new recommendations and its respective weights were defined for the LF_grade, and the lead-free process factor (П𝐿𝐹) equation was simplified respecting the value range (from 1 to 2) proposed by FIDES; therefore, the lead-free process factor (П𝐿𝐹) can double the failure rate predicted (λ).

It is necessary to consider that currently there is a need to predict reliability applying an updated lead-free factor that identify and control the factors that presently influence the reliability are even more important objectives. Key Words: Failure rate, FIDES, lead-free, Pb-free, pi-factors, reliability prediction

Over many years defect analysis has been used at the company to determine the root cause of various defects experienced in the field on electronic products from customers. Based on this work it has been found that around 25 percent of all case studies have been due to de-wetting issues.

De-wetting is an issue with the solder joint where the molten solder and the substrate/component repel each other during the soldering process. Due to this a very weak or no intermetallic bond is formed at the interface after reflow leading to defective and unreliable solder joints.

Case studies in this area will be reviewed based on root cause analysis and countermeasures to prevent these defects. These case studies are related to inferior component/board plating quality, contaminated plating on both the PCB as well as the component, Foreign Object Debris (FOD) as a cause of the de-wetting of solder, damaged component plating and improper off-set solder paste printing. The results of the failure analysis are reported.

Two independent Printed Circuit Board (PCB) suppliers found unusually high voiding anomalies in multiple manufacturing lots of PCBs that were processed over a 5 month period. The issue was noted during conformance coupon inspection of an initial lot, and subsequently determined to be isolated to the prepregnated portion of pure polyimide constructions in a number of PCB manufacturing lots. During the study, the team investigated numerous variables potentially associated with the root cause of the anomaly, including but not limited to: raw materials, conformance coupon preparation, and processing issues. The objective of this paper is to describe the approaches and techniques used in this void anomaly case history when requirements are not always clearly stated.

An initial review meeting was requested by one of the PCB suppliers and was attended by: the PCB manufacturer, procuring activity, design agent, and raw material manufacturer. The purpose of the meeting was to identify the anomalies, categorize them, and determine acceptability based on product specifications. Also addressed during the review were potential impacts to product functionality. The following categories were used for anomaly identification: glass tear out, void/striation, bundle cracks, foreign material, and unknown. The categorization was conducted to help the team determine the appropriate acceptability criteria for each attribute. A pareto analysis indicted that the top two anomalies observed were void/striation and glass tear out. In many cases, it was difficult to determine the difference between the two. A striation (or tunnel void) is a void in the resin between the filaments of the fiberglass bundle. A tear out is a condition where sections of glass bundles are removed from the potted coupon, as a result of coupon preparation (grinding and polishing). Based on MIL-PRF-31032/1 (2020), voids/striations are a rejectable condition if they are out of the thermal zone, and the condition is greater than .08 mm, and/or reduces the dielectric to below the minimum requirement. Upon further investigation, it was found that the anomalies were potentially related to the glass style used in the prepregnated layers.

This paper provides a methodical approach to investigating particular anomalies in PCBs to determine acceptability. It may be utilized as a guideline for others facing a similar anomalies associated with PCBs.