No two printed circuit boards look exactly alike. Even across two adjacent boards on an assembly line,one can find
significant differences arising out of normal process variation – the components and the boards can change color,size and
surface markings. A key challenge for inspection systems is to automatically handle such allowable variation,and distinguish
it from other variations that constitute defects.
Automated optical inspection (AOI) systems have emerged as an important test strategy in printed circuit board
manufacturing to detect defects. Typical AOI systems depend in large measure on heuristics-based (trial and error
experimentation) data as the means to establish typical conditions,the degree of normal variation,the thresholds for nominal
pass/fail conditions,the lighting/camera conditions to best view the object,and the parameters for providing variable
measurement data. The use of empirical processes is a sound basis to make decisions where the sample population being
employed is large enough to mimic the whole. However,user assessments of heuristics require skill and experience of
programmers. As a result,the competency of empirical methods is built up over time and over volume by basing ‘goodness’
criteria on historical values and historical volumes,as seen through the filter of user judgment. Where time and volume are
insufficient to establish stable norms,where user judgment of good and bad are questionable,or where variation of the
elements of the printed circuit board is significant,it becomes difficult to effectively deploy heuristic-based programs.
In this paper,we present a new technology called ‘Configural Recognition’ that provides built-in tolerance to normal process
variation. The technology was initially developed at the MIT Artificial Intelligence Laboratory for applications such as
natural scene classification,face recognition,and trademark logo search. In these applications,normal variation is a
significant and challenging problem for standard computer-vision systems. The technology is grounded in studies of how
humans visually recognize objects.
Over the past six years the technology has been employed for the task of printed circuit board inspection and process control.
The benefits of the technology in the PCB domain are its native ability to recognize PCB artifacts without re-sensitizing the
objects under test,thus eliminating or reducing the necessity of establishing test norms A second benefit is that as variation is
a known entity and accepted as an inevitable but compensated activity,far fewer examples need be used to generate a PCB
test program. Finally,the technology allows for the optical-inspection system to make the leap from finding defects to
providing reliable and repeatable variable measurement data with the same ease of use.

Consistently achieving acceptable wave solder through-hole fill on thick boards is a well-known process challenge,but the
introduction of lead free solders has created additional difficulties. There are many reasons why one might achieve lower fill
with lead free solders and there is much room for improvement in flux materials and process development,but unnecessary
scrap and rework may be avoided by allowing lower barrel fill in some cases.
Most OEMs have a waiver process to allow lower barrel fill than required by IPC-A-610D Acceptability of Electronic
Assemblies for individual holes,but it seemed critical to gather more information for lead free solders in order to support the
possibility of lowering the fill requirements for more boards and components by class. This study updated the previous work
that had been done on through-hole reliability by considering joints made with Sn-3.0Ag-0.5Cu (SAC305) solder and a range
of fill percents,including lower fill percents than are required by IPC-A-610D.
SAC305 through-hole joints (with components loaded) were soldered on 0.062",0.097",and 0.130" thick boards,with fill
percents between 10% and 100%. These boards were subjected to thermal cycling,shock or vibration. After the stress
exposure,the pull strengths of the joints were measured.
The data showed that pin wetted length correlates well with the pull strengths of through-hole joints for different PCB
thicknesses. Shock and vibration were the most detrimental stressors in the range tested. Minimum fill requirements were
determined,based on board thicknesses and load per pin. This work has shown that lower fill levels than are sometimes
required by IPC-A-610D will produce reliable SAC solder joints.

The New England Lead-free Electronics Consortium is a collaborative effort of New England companies spanning the
electronics supply chain,sponsored by the Toxics Use Reduction Institute,the U.S. EPA,and the University of
Massachusetts Lowell. The consortium has completed and published the results of two phases of manufacturing and testing
of lead-free Printed Wiring Boards (PWBs) with the goal of achieving zero-defect lead-free soldering processes with
comparable reliability to that of leaded solder processes. Phase I examined various solder alloy combinations and reflow
profiles,while Phase II focused more broadly on processing parameters,utilizing a mix of component types and finishes in
combination with five different PWB finishes,two reflow atmospheres (air and nitrogen) and three solder paste compositions
based on the same Sn3.8Ag0.7Cu alloy.
Phase III efforts began in August 2004 and will be completed by November 2005. The objective for Phase III testing is to
focus on implementation issues by simulating an actual production board for parameters such as board layers,board size,and
component density. The Phase III PWB is a twenty layer board with components on both sides,and populated with 1,750
components. Thirty-six PWBs were built and inspected to IPC 610 D standards by Benchmark Electronics in April 2005.
The PWBs underwent thermal cycling at Raytheon Reliability Labs test facilities and Highly Accelerated Life Testing
(HALT) at Teradyne test facilities. Pull testing was conducted at the University of Massachusetts Lowell. In this paper,the
authors will present the results of Phase III efforts,including the PWB interconnect stress test,test coupon failure mode
analysis,visual inspection,thermal cycling,HALT,and pull tests.

For this study,researchers from the University of Toronto produced samples of Sn-Pb solder,with additions of bismuth,
solidified at controlled cooling rates. The microstructure of the various Bi content and cooling rate combinations is analyzed.
Limiting conditions for the occurrence of the Sn-Pb-Bi ternary eutectic are discussed. A team from Celestica produced two
sets of test vehicle assemblies using both Pb-free and eutectic SnPb solder. The first set of assemblies includes combinations
of three PWB surface finishes (OSP,Immersion Ag,ENIG) and three component lead finishes (Sn-Pb,Sn-Bi,Ni-Pd-Au).
Microstructures,intermetallic type,composition,and thickness after assembly,aging,and 0°C to 100°C thermal cycling were
studied. Pull testing was performed on QFPs and TQFPs to evaluate the tensile strength of solder joints as assembled and
after thermal aging and vibration conditioning. The second set of assemblies was subjected to 6000 ATC cycles 0C to 100C.
Results are provided for TQFP 0.5 mm and TQFP 0.4 mm devices on ENIG boards. The conclusions on combinations of
solder pastes,surface finishes and component terminations are discussed.

Flexible circuit interconnects for ultrasound transducer applications are among the most difficult to fabricate and make good
representative circuits for medical applications. The polyimide dielectric can be as thin as 12 micron. They often contain
ultra-high density regions that are push the edge of currently available technology. Lines and spaces can be as small as 20 to
30 micron,and via diameters can be as small as 25 micron. The interconnects are typically fabricated starting with
adhesiveless copper on polyimide flexible substrates manufactured using sputtering and electroplating techniques. High
performance polyimides provide mechanical and thermal stability needed to metallize thin dielectric without significant
wrinkling or creasing. The availability of thin copper and smooth interfaces facilitates fine-line etching and high density
features. Good adhesion is critical to ensure fine-line features remain intact throughout the fabrication process. Peel strength
exceeding 6 lb/in is achieved by pretreating the polyimide surface with plasma and applying a suitable tiecoat metal between
copper and polyimide. Laminate dimensional stability after etching and heating exceeds the IPC specification and promotes
good alignment and registration of circuit features. Fine-line features imply strict copper quality requirements. Pinholes
represent an important aspect of copper quality. Systematic analyses have been done to classify pinholes and link different
types to their likely causes. The classification scheme and detailed analyses serve as a basis for pinhole quality control in the
manufacturing environment. The approach has been used to help reduce pinholes and serves to allow rapid containment if
pinholes become an issue.

Flexible printed circuits are a growing technology both in terms of numbers and in technology advancement. Applied as
cabling harness technology,IC packaging and as replacement for rigid board technologies,more designs are based on flexible
substrates than ever and the numbers are rapidly growing. As density and layer count increases,so do the concerns about
reliability and yield.
Proper care must be taken to ensure that the many risk factors in Flex manufacturing are kept under control. Layer stackup,
adhesives,dielectrics,stiffeners,cover layers,bend and flex,width transitions,trace curves,embedded components are all
well known factors in Flex design and manufacturing where each and every one requires special considerations.
Obviously,these factors have to be considered early in the design cycle as in all engineering: issues discovered late in the
process become extremely costly.
In this paper,we will look at all of these areas and how new CAD technology can assist in keeping these effects under
control.
Bend region stress,reliability and restrictions,adhesion concerns,layer stackup management together with design efficiency
issues such as effective trace routing in complex curved regions will be covered in detail.
We will show that although Flex technology is becoming more and more advanced,given the proper precautions,yield,
reliability and design efficiency can still be kept at a convincing high.

The kinetics of activator disappearance were investigated for a wave-soldering flux containing two activators,succinic and
glutaric acids. Three loadings of flux were applied to bare FR4 panels and copper-clad laminate coated with an organic
soldering protector (OSP),then baked at 110°C,95°C,80°C and 65°C for different times. The flux activator acids remaining
after baking were analyzed by ion chromatography. The experimental results were analyzed assuming 1st order kinetics of
acid disappearance and the Arrhenius equation. These results suggest:
• Glutaric acid disappears about 8 times faster than succinic acid on bare FR4 and about 2.5 times faster on OSP
panels.
• From the accelerated predictions,rates of glutaric and succinic acid disappearance on FR4 and OSP were
extrapolated for 40°C,and expected loss of these acids have been estimated as a function of time. While the glutaric
acid activator on both surfaces is 99% deactivated in 3 weeks at 40°C,the succinic acid requires 4.9 years for 99%
of the original amount to disappear at 40°C on bare FR4,but only 10 months at 40ºC on OSP.
• The measured actual rates of glutaric acid disappearance at 40ºC on bare FR4 and OSP were about ½ of the
predicted rates. The actual rate of disappearance of succinic acid at 40ºC on FR4 was about 6 times faster than the
extrapolated value. The 99% deactivation at 40°C for both acids on both surfaces have been calculated,and are 1.5
months for glutaric acid on both surfaces,one year for succinic acid on FR4 and 3.5 months for succinic acid on
OSP.

A fluxless bonding process between silicon and copper using Sn-rich Ag-Sn-Au multilayer composite has been developed.
The copper substrate is plated with a silver layer as stress buffer. We bond 5mm x 5mm silicon chips onto Ag/copper
substrates using electroplated lead-free Ag-Sn-Au solder. Electroplating method becomes an attractive deposition technique
in that thicker films can be fabricated. It also has an economical advantage over vacuum deposition technique. To achieve
high quality joint with few voids,a fluxless bonding process is developed in vacuum environment (50 militorrs) to suppress
tin oxidation. Comparing to bonding in air,the oxygen content is reduced by a factor of 15,200. Nearly void-free solder joints
are made. Initial joints comprising of three distinct layers of Sn-rich layer,Ag3Sn intermetallic compound,and Ag layer have
been achieved. Microstructure and composition of the joint are studied using optical microscope and Scanning Electron
Microscope (SEM) with energy dispersive X-ray spectroscopy (EDX). This technique becomes an innovative success for
overcoming the very large mismatch in thermal expansion between silicon of 3x10-6ppm/°C and copper of 17x10-6ppm/°C.
To evaluate the reliability of the solder joint and the bonded structure,samples will go through thermal cycling test and
failure modes will be evaluated in the future. Microstructural changes of the solder joints during thermal cycling test will be
investigated and assessed. Based on the results obtained,design recommendation can be made for producing joints with high
re-melting temperature.

The American Competitiveness Institute (ACI) performed a series of Environmental Stress Tests for the Joint Group of
Pollution Prevention / Joint Council of Aging Aircraft (JG-PP / JCAA) Lead Free Soldering Program. The objective was to
determine if Lead Free soldered hardware was equivalent to or better than its Tin Lead (SnPb) counterpart. The program’s
test vehicle was manufactured by BAE Systems in Irvine,Texas. The JG-PP / JCAA test vehicle was soldered with Tin Lead
(SnPb) as a baseline,Tin Silver Copper (95.5Sn3.9Ag0.6Cu or SAC),Tin Silver Copper Bismuth ((92.3Sn3.4Ag1.0Cu3.3Bi
or SACB),and stabilized Tin Copper (99.3Sn0.7Cu0.05Ni).
The Salt Atmosphere test was performed in accordance to ASTM B117 Test Method for 48 hours. The Temperature
Humidity test followed the procedure MIL-STD 810F; Test Method 507.4. In both tests,no failures were found that could be
attributed to the solder joints. Therefore,the Tin Lead and Lead Free soldered hardware can be considered equivalent.
Two types of Mechanical Shock tests were performed. The first Mechanical Shock test was performed using the test
procedure MIL-STD 810F; Method 516.5; Procedure 1. The test was performed on all 3 axes. 2 components soldered with
SACB failed the tests. The balance of the SnPb and Lead Free soldered components passed this mechanical shock test with
no failures.
The second Mechanical Shock test was performed to a modified version of MIL-STD 810F; Method 516.5; Procedure 1,
where the test vehicle was tested in the Z-Direction,at increasing levels to failure. The mechanical shock levels reached in
this test were above those in the first mechanical shock test. Across all test levels and component types,the SnPb soldered
hardware performed comparable or better than the SAC and the SACB soldered hardware.

Vibration testing was conducted by Boeing Phantom Works (Seattle) for the Joint Council on Aging Aircraft/Joint Group on
Pollution Prevention (JCAA/JG-PP) No-Lead Solder Project. The JCAA/JG-PP Consortium is the first group to test the
reliability of lead-free solder joints against the requirements of the aerospace/military community.
A complete modal analysis was conducted on one test vehicle (the “Pathfinder” PWA) using a laser vibrometer system. This
system measured velocities,accelerations and displacements of the PWA during the vibration test. The laser vibrometer data
was used to determine the resonant frequencies of the “Pathfinder” PWA and the actual deflection shapes of the PWA during
test. In addition,the strains generated during a 1 G sine dwell were calculated for 1189 points on the “Pathfinder” PWA.
After completion of the modal analysis,thirty test vehicles (in two batches of 15 test vehicles each) were subjected to the
vibration test conditions. The input power spectral density was increased during the test at 60 minute intervals in an effort to
fail as many components as possible within the time allotted for the test.
The solder joints on the components were electrically monitored using event detectors and any solder joint failures were
recorded on a Labview-based data collection system. The time to failure of a given component attached with SnPb solder
was then compared to the time to failure of the same component attached with lead-free solders.
After completion of the testing,all of the test vehicles were visually inspected. Broken component leads and other unwanted
failure modes were documented.