Physical Implementation of the High-Speed Design Process
Layout designers play a critical role in the design of high-speed circuits. In an optimized process,they take constraints
defined by engineering and create a layout that adheres to those design rules. Typically,however,the process is more ad hoc
with constraints being transferred via paper or voice,putting more responsibility on the layout designer to translate the
requirements and implement a functional design. In some organizations,engineering has taken over layout of high-speed
signals to ensure accurate implementation of constraints. Unfortunately,this often results in designs that are impossible to
complete or are un-manufacturable.
Today's complex designs can have advanced constraints on 80-90% of the board's signals,significantly increasing the layout
difficulty and design cycle time. To appropriately manage and implement these constraints,layout designers must
understand concepts such as differential impedance/signaling,star net topologies,interconnect delay and crosstalk coupling.
This paper will address:
• High-speed constraint categories in “electrical” and “physical” incarnations
• An optimized design process focusing on collaboration between engineering and layout departments
• Routing best practices to adhere to advanced high-speed constraints
• The impact/benefit of advanced fabrication technologies like HDI and embedded passives on high-speed design.