The Evolution of Any Layer IVH Structure PWB

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With the advent of digitisation,networking,broadband telecommunication,and miniaturization in electronic set products,electronic devices are essentially required to deliver high electrical and mechanical performance that correspond with this trend. From its first introduction in 1996,Any Layer IVH structure ALIVH has been serving the mobile phone application as its core business market but has since diversified into several other markets. Therefore,I would like to give an introduction,along with an update on the status of ALIVH for motherboard use and the technological development and trends of our extended range of new products such as ALIVH -B,ALIVH (G-type),etc

Author(s)
Satoshi Maezawa
Resource Type
Technical Paper
Event
IPC Fall Meetings 2002

Yield Enhancement in BGA Substrates and Packaging

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The growing use of high density interconnect (HDI) substrates in the microelectronics packaging industry has brought along a broad range of yield issues. Many of these issues are associated with surface defects in the interconnect terminals and solder mask areas of the finished substrates. Detecting such defects requires a different set of capabilities than that of traditional Automated Optical Inspection (AOI) tools used for in-process inspection. These differences result in particular from the surface integrity specifications of the interconnect terminals,and the subjectivity of defect severity. This paper presents examples of defects and discusses inspection capabilities required to detect and classify them correctly. It examines the factors affecting detection capability and false alarms,and proposes a simplified method for system performance evaluation and setup optimization.

Author(s)
Yossi Pinhassi,Udi Efrat,Moti Yanuka
Resource Type
Technical Paper
Event
IPC Fall Meetings 2002

The Era of the 3-D System In Package (SIP) will be Ushered in by Japanese Mobile Phones

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It is becoming impossible to realize the latest mobile phones and other mobile equipment without Chip Size Packages (CSP) and other high-density semiconductor package technology. At present,the most advanced mobile phones in the world are being made in Japan with a compact size and lightweight,but these rely for the most part on chip stacked CSP technology. This paper describes how mobile phone packaging technology has changed in Japan,from 1996 to 2001-2002,and how packaging is being done in the most recent mobile phones. In preparation for the coming era of 3-D System In Package (3-D SIP),this paper also describes the kind of technologies that are possible today,and how they will develop in the future.

Author(s)
Morihiro Kada
Resource Type
Technical Paper
Event
IPC Fall Meetings 2002

Advanced Packaging Using Liquid Crystalline Polymer (LCP) Substrates

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Liquid crystalline polymer (LCP) substrates offer a number of advantages for high-density packaging. These properties include high temperature capability (>250oC),low coefficient of thermal expansion (8ppm/ oC),low moisture permeability (comparable to glass),smooth surface,and good high frequency characteristics. LCP substrates can be fabricated as flexible films (2mil thick) or as rigid multilayer substrates. In this paper the processing of rigid and flexible LCP substrates are first discussed including etching,drilling,and plating. Next,the compatibility of LCP substrates with wire bond and flip chip assembly processes and materials are examined. Specific tests include solderability with eutectic Sn/Pb and lead-free alloys,surface insulation resistance with no clean fluxes,gold wire bondability and flow/wetting of underfills for flip chip assembly. The high temperature capability of the LCP is compatible with the higher reflow temperatures associated with lead–free solders and also allows thermosonic gold wire bonding at a substrate temperature of 200oC. Solder dips in lead free alloys at 274oC have shown no delamination of the copper foil. Gold ball shear test results demonstrate average shear strength of 62.4 grams with a standard deviation of 4.3 grams when bonded at 200oC. Optical fibers can be molded into the LCP substrate for optical connections and optical fibers can also be molded into the package sidewall for optical connections. Finally,hermetic packages have been fabricated and shown to pass fine and gross leak tests.

Author(s)
Tan Zhang,Wayne Johnson,Brian Farrell,Michael St. Lawrence
Resource Type
Technical Paper
Event
IPC Fall Meetings 2002

Overcoming Technical and Business Issues Associated with System in Package Adoption

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In today's world of electronics the keywords are smaller,faster and cheaper. With more and more circuitry going onto existing circuit boards,the designers are searching for ways to contain this additional functionality in the same,or smaller,space envelope. To accomplish this,the semiconductor die used in the circuit design must shed the traditional packaging enclosures. One solution is to create sub-systems as building blocks that can be assembled on a motherboard to provide a complete functional solution. Twenty years ago we called these sub-systems “Hybrids”. When the die became larger than the discretes,we called them MCM’s. While searching for a descriptor for MCM,it was suggested that “if you can’t afford it,it must be an MCM)”. Now “system in a package” is in vogue. Many of the issues faced twenty years ago are still issues today. However,more have been added. These of course include die quality and reliability including tradeoffs,assembly quality and reworkability and in some cases substrate quality and reliability. This paper primarily looks at die quality and reliability issues and discusses solutions or work-arounds.

Author(s)
Jim Rates
Resource Type
Technical Paper
Event
IPC Fall Meetings 2002

Programming Considerations in Complex Wave Form Pulse Reverse Plating: Part 1,Developing the Tool

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With the advent of more flexible versions of pulse-reverse plating technologies,and with the ability to program more of the waveform parameters,comes an increased number of options facing the user. An impediment to the rapid determination of the optimum programming parameters in any via-plating system is the very large numbers of test runs this can generate,and the very time-consuming cross-section evaluations needed to assure that valid decisions are made. Similarly,this “cross-section proliferation” problem faces platers contemplating any other plating process options (eductor placement,vibration equipment,agitation changes,chemical changes,etc.) Building on an idea put forward by Yair Assaf at AESF SurFin 2002,this paper reports on experimentation using a test unit to allow programs to be pre-screened without cross-section verification,in comparison with conventional cross-section evaluation. The test unit is designed to be used by itself,or to accompany parts through the plating cycle,and consists of a tapered-gap,with a removable copper tape as plating substrate. All this is to permit better/faster/less burdensome realization of the benefits of complex wave form pulse reverse systems in via formation. It is our hope that others in the industry will expand on this idea to the point that it can be developed into a useful,reliable tool.

Author(s)
Marc Carter
Resource Type
Technical Paper
Event
IPC Fall Meetings 2002