For high reliability applications,the use of x-ray technique has become an additional inspection requirement for
quality control and detection of unique defects due to manufacturing of advanced electronic packages such as ball
grid array (BGAs) and chip scale packages (CSPs). Recently,four x-ray systems were evaluated for their defect
detection capability,especially for damage/cracks induced during thermal cycling of ceramic column grid array
(CCGA)/BGA assemblies. These systems were:
1. Case 1: A 2D real time x-ray with a microfocus source and image intensifier as detector. For this case,position
of detector to x-ray source is a straight line.
2. Case 2: A 2D system with x-ray transmission similar to the case 1 with the exception of detector had off-axis
rotational capability,therefore; providing oblique views at higher magnifications.
3. Case 3: A fully digital tomosynthesis x-ray system that is capable to combine 3D volumetric imaging and
conventional 2D x-ray for a complete inspection.
4. Case 4: A custom made 3D computed tomography (CT) x-ray system. It utilizes a high power microfocus
source (cone and parallel beam) and glass scintillator detector or flat panel digital detector to obtain crosssectional
2D x-ray images with preprogrammed angle views. The reconstruction algorithm then provides a true
3D volumetric display
This paper discusses limitation of each system and provides representative inspection images for CCGA/BGA
assemblies. The assemblies have subjected to various thermal cycle and ranges and have shown different levels of
damage/cracking. The x-ray images were compared to optical images taken by a 3D optical microscopy for outer
rows of array package assemblies.

The advent of miniature surface mount components coupled with increasing lead counts has posed tremendous
challenges during assembly. This is especially true in an Electronics Manufacturing Service (EMS) industry where
the focus has been to increase throughput and first pass yields at lowest cost. Therefore,robust and repeatable
inspection systems need to be employed in order to achieve these objectives. Due to the constraints imposed by the
existing inspection technologies,the effectiveness of automated x-ray inspection system was investigated from a
statistical and assembly perspective. The results were analyzed and significant measures were initiated and
employed to improve the performance of the automated x-ray inspection system and subsequently of the Surface
Mount Technology (SMT) line.

This paper will discuss:
a. Boundary scan as a key test tool that enables the leveraged test approach
b. The advantages of standardizing and reusing design verification tests and PLD programs in the manufacturing
test environment
c. Issues related to the hardware and software infrastructure required to achieve efficient test portability
d. DFT guidelines and other recommendations to improve the linkages between product design,prototype
verification,and high-volume manufacturing tests
e. Case studies demonstrating effective boundary-scan test strategies from design to manufacturing

Boundary-scan has achieved many of the goals envisioned by its original architects and today is in use in thousands
of production facilities around the world to test complex digital printed circuit boards. The original vision of the
IEEE 1149.1 specification,to restore test access and fault coverage to assemblies with few physical test points
relative to the number of electrical nets to be tested,has been attained. Ongoing advances in chip design,system
architecture,and application development tools are extending the power of boundary-scan to support the
implementation of solutions at the system-level as well as the board level.
The rationale for deploying boundary-scan technology within the system hierarchy is described in this paper.
Applications include:
• Providing single-point access to multiple scan chains for testing and in-system programming
• System checkout prior to shipping,including verification of board presence
• Configuring the system for customer-specific requirements
• Testing of system backplane or other interconnection means
• Environmental stress testing
A variety of system-level boundary-scan topologies are available,utilizing the many scan-compatible bridging
devices on the market. This paper will describe the various methods,including multi-drop architecture in which all
boundary-scan signals are routed to all boards within a system environment via a backplane bus,thereby supporting
comprehensive test capabilities. The application of boundary-scan to provide a coherent test capability both at the
board- and system-level will be described. The paper also describes how a carefully considered test strategy,
implemented at design concept,can support a product throughout its complete life cycle.
An example of a successful system level implementation is provided to demonstrate how 1149.1 can be utilized to
solve a wide range of manufacturing problems and for providing comprehensive system level diagnosis.

In recent years,technological advances in electronics manufacturing have allowed high volume manufacturers to
significantly improve process control and documentation. Manufacturers have accelerated the use of solder paste
and component vision systems,x-ray analysis,and in-circuit feedback systems to drive manufacturing defects to low
parts per million (ppm) levels. One of the latest opportunities for delivering improved process yields is in the control
and documentation of the reflow environment.
This paper investigates the use of comprehensive reflow profiling systems to control the reflow temperatures within
the reflow environment and document the temperature range for specific locations on a printed circuit assembly. The
analysis will also evaluate the capability of the automated reflow monitoring system to accurately measure thermal
regions within the oven over a wide variety of profiles,board designs,materials,and production volume. Finally,
this analysis investigates the impact of temperature control on solder joint quality using several different solders and
substrate materials.

The drive for electronic devices to become lightweight,more portable,and posses increased functionality has driven
electronic components to smaller and smaller sizes. This decease in size does not only apply to active devices such
as chip scale packages (CSPs) and area array devices,but also to discrete components,such as capacitors and
resistors. This has lead to an increase in the use of 0402 and 0201 sized components. These components represent a
significant decrease in size from other discrete components. The major challenge with these components is typically
issues with processing. One of the most common defects associated with these small components is tombstoning. A
variety of solutions have been proposed for reducing or eliminating tombstoning. To date these have mostly been
changes in design and/or processing. Implementing these changes after production has begun can be costly and time
consuming. Also,even if some of these changes are implemented other process factors can contribute to an increase
in tombstoning. This paper presents a materials based solution to the tombstoning issue. This solution widens the
process window with respect to tombstoning and has been used to reduce the occurrence of tombstones in
production. Causes of tombstoning,case studies,and the mechanism behind how the material reduces tombstoning
will be presented.

Solder beading and tombstoning are observed increasingly with chip components as their size decreases. This is
even more crucial in today’s packaging,due to the high ratio of passive components in comparison to active
components. The increasing number of passive components affects the Defects Per Million Opportunities (DPMO),
which inturn affects the overall yield of the assembly line. Hence,it is vital to understand the various causes within
the assembly process,which influence the occurrence of these defects. This paper will discuss the results of a
process characterization study to understand the effects of solder paste,stencil thickness,board support,reflow
profile and the component size on the formation of solder beads and tombstones. A Resolution-V DOE analysis was
performed to determine the effect of these factors on the defect occurrence. The response variable for the study was
% defects,the ratio of number of defect occurrences to the total number of available defect opportunities.

The trend in electronics packaging towards product miniaturization,has forced the industry to use fine pitch area
array packages instead of fine pitch leaded packages. These area array packages enable higher production yields and
are less prone to handling damages,thereby enhancing the system throughput. Incorporating these packages into the
assembly and also achieving the required process robustness,requires a thorough understanding of the process
variables and the ability to control them.
As indicated in various research publications,the solder paste print process is very critical to the assembly of these
packages. This process contributes to 60-70% of the assembly defects. Hence,the Center for Electronics
Manufacturing and Assembly at RIT undertook an investigative study,using Taguchi techniques,to identify the
critical factors and improve the robustness of the stencil printing process,for fine pitch area array packages.
Taguchi’s robust design technique is a viable analysis tool for evaluating complex processes that involve a multitude
of variables. Prior process knowledge is required to understand the effect of various parameters and the results of
Taguchi experiment.
The Taguchi analysis utilizes signal to noise ratio calculations to reveal the effect of process variables such as print
pressure,print stroke and separation speed,on paste volume variability and % transfer. Details of this study and the
analysis are presented in this paper. Significant conclusions about board finish,aperture size and shape and stencil
manufacturing technology were inferred and are discussed in the paper. Moreover,this case study can serve as a
quick reference to perform Taguchi analyses for similar process studies.

Quantitative solder paste performance or use testing enables material formulators to focus on and maximize key
material traits such as wettability and printability. These same material test methods and tools allow SMT engineers
to fine tune reflow profiles,stencil aperture design and specific print parameters. A fourth generation multi-purpose
test vehicle design has been developed and is discussed in detail. Specific quantitative tests for printability,abandon
time,wettability,slump,solder beading and balling,tombstoning,pin testability and X-ray voiding have been
incorporated into one test board. Methods to extract quantitative data and “score” a material for objective
comparisons are discussed.

Today’s SMT assemblies are being driven toward SMD’s with higher lead densities as well as smaller packages.
This places additional performance requirements on the printing process. The stencil printing process has a major
influence on SMT assembly yields. It is important to consider stencil design,aperture design,and stencil printing
performance when selecting a stencil. This paper will focus on stencil printing performance and,specifically,how to
choose the correct stencil to increase SMT assembly yields.
Stencil print performance is evaluated over a range of stencil technologies including: Electroform,Laser-cut,Lasercut
with Electropolish and Nickel plate,and Precision Chemically - milled stencils. A total of 23 different stencils
were evaluated in the study. These stencils are made using the exact same Gerber file. Stencil printer set-up,solder
paste,and solder volume measurement set-up is identical for the stencils. Print studies were performed in an
independent test laboratory. Solder volume is measured for 8 different device types,including the following: 0201,
uBGA 20 mil pitch,0402,CBGA 40 mil pitch,16,20,25 mil pitch QFP’s and uBGA 31mil pitch. Stencil print
performance will be evaluated by measuring solder paste volume,solder paste volume dispersion,misprints
(bridging or insufficients) and positional accuracy of the stencil apertures. Physical properties of each stencil such as
aperture size,aperture wall smoothness and aperture cross section are measured. This information will be used to
predict SMT assembly yields for the array device types listed above. The yield data is then used to predict rework
cost related to the different types of stencils included in the study. Paste relax and recovery tests using three solder
paste types and five stencil types is reported. In this test dwell time between prints is varied from 15 minutes to 90
minutes.