In high speed digital interconnects; signal attenuation is a result of both dielectric losses and conductor losses. Previous
works have showed in detail,the characterization and modeling efforts regarding the impact of dielectric loss in PCBs and
the differences between various dielectric materials. Most high speed characterization modeling efforts have not
encompassed the variations in conductor losses due to variations in copper foil roughness or treatments of copper foil for
adhesion. Several recent publications have reported frequency dependent copper losses that do not follow the classical square
root relationship. This paper presents the results for a set of high frequency loss characterizations across various copper foils
and the impact of the copper roughness on the relationship between conductor loss and frequency. Also discussed in this
paper are the implications in high frequency modeling resulting from non-classical conductor losses and the requirements to
ensure causality in simulation results.

Demand for higher speed digital signal processing is notable today in the electronics industry. To meet this demand,circuit
designs that employ coplanar structure,either for both single-end and differential transmission,are increasing. The purpose of
coplanar structure is mostly cross-talk (noise) reduction. It is mostly the case that guard-earth lines are added to microstrip
line or strip line structure to make coplanar structure. However,electro-magnetic field tends to be very complicated for such
structures,and so how the structure is related to characteristic impedance or cross-talk is not well understood yet. For
example,there are some cases where characteristic impedance would be 30% or more different by adding coplanar lines to
simple micro-strip line structure. In these cases,conventional methods will not work well to predict characteristic impedance
with sufficient accuracy. What is making it so difficult is the complicating relation between the signal line references to the
ground layer and to the coplanar lines,and so understanding the electro-magnetic reference mechanism with coplanar
structure is essential to achieve good enough control of characteristic impedance,noise,and cross-talks. We made a detailed
analysis on a coplanar structure and worked out an explanation as to the mechanism with a simple,practical coplanar
structure. In this paper,details of our study on coplanar structures shall be reported,with some proposals as to the design of
coplanar pattern in terms of cross-talk reduction.

Electronic products are being stressed by increasing operating temperatures and higher assembly temperatures. Silicon and
product power consumption are increasing as the silicon densities and signaling frequencies increase. And,the transition to
lead-free solders is resulting in higher thermal excursions during assembly. Both of these conditions are impacting material
selection during product design and are having an impact on product qualification,and influencing long term via reliability.
This paper details the results of an Intel investigation of printed circuit board materials,fabrication processes,and design
variables and the resulting impact on board reliability after lead-free assembly. Results were baselined against standard tinlead
assembly for purposes of comparison. Printed circuit board process and design variables examined included via size,
layer count,board thickness,and laminate material. Also examined were the variation within an individual supplier and the
variation across multiple suppliers using the same materials. The paper details the test board configurations used in the study,
the lead-free and tin-lead assembly profiles to which the boards were subjected,and the test methods employed to collect the
data. The test data highlights key trends in the reliability data as a function of changes in the variables tested.

Lead products are no longer an option if you want to export to the EU market. RoHS regulations requiring the manufacture of
lead-free electronic products by July 2006 are pushing the industry to evaluate and find lead free solutions soon. There are
several important issues in undertaking a transition to lead free,including: 1) finding PCB materials and plating finishes that
can withstand the high reflow and wave temperatures of lead free alloys,2) selecting lead free alloys that have similar or
better quality and reliability characteristics than SnPb,3) assessing whether the lead-free components can withstand high
reflow temperatures,4) finding a cost effective solution,and 5) understanding and solving the challenges of the lead-free
process on PCBs,components and solder joint quality. In this paper we address these issues by evaluating a) two PCB
materia ls - FR1 and FR4,b) PCB plating finish – OSP and Ni/Au,c) lead-free alloy Sn 3.5Ag0.5Cu (SAC) and 58Bi42Sn,
and d) the number of reflows (single -sided vs. double-sided). We evaluated 58Bi42Sn eutectic alloy as a solution for those
components that cannot withstand the high temperature process of SAC alloy. Our goal is to determine a cost effective
solution for a low temperature application. Different reliability tests,warpage measurements,and cross sections were used to
evaluate each configuration.

Environmental regulations are forcing the elimination of lead (Pb) from electronic equipment. 2005 will be the year that
many electronics assemblers will be transitioning their soldering processes from traditional tin-lead alloys to lead-free alloys.
Many alternatives to tin-lead have been proven to be technically viable in relatively small volumes,but the implementation of
the new processes in high-volume manufacturing presents a series of new challenges to engineering and operations personnel.
This paper reviews six major considerations for implementing lead-free soldering processes in a manufacturing operation:
equipment evaluation,materials compatibility,separating and identifying the two separate processes,training,validating the
process,and beginning continual improvement. Details of each consideration are discussed and summarized in a checklist
format at the end of the paper.

In the multilayer PCB industry,the process of making the inner layer is the first step in a number of complex steps that
results in the production of a printed wiring board. This imaging manufacturing step comprises of a number of subprocesses
that together allow for the metal interconnect pattern to be formed. The steps by themselves are small and can seem
irrelevant,however a good balance of precision and synchronization of all processes is required to guarantee a high yielding
reproduction of the circuitry pattern. To ensure the process has the ability to function in any of the selected production
environment the selection of raw materials is key to the functionality of the chosen photoresist.
20 years ago,the Inner Layer Photoresist market is being dominated by dry film. However in recent years a significant move
towards liquid photoresist has been noted. The main drive for liquid resist was the increased needs for resolution without the
need for investment in new equipment. The cost of dry film is relatively high and cannot match the low cost and high
resolution of today’s liquid resist market offerings.
The industry is demanding a leading edge liquid resist that can balance the formulation of the raw materials used to a ensure a
low cost resist formulation that can maintain stable,reproducible,high yielding processes that work in conjunction with the
various equipment sets used in the industry today.
In this paper,the first section will be allocated to a discussion on the various equipment / process issues. The second section
will be focused on the trade offs in formulation to meet those requirements. The final section will discuss the engineering of a
formulation that address the issues discussed.

Next generation IC substrate designs will feature higher interconnect density and faster signal speed than current designs.
Circuitization of these substrates uses copper pattern plating followed by differential etching,which is called “semi-additive
processing”. Dry film photoresist is well suited for semi-additive processing because it is available at the proper resist
thickness with excellent thickness uniformity.
The performance requirements for dry film photoresist for semi-additive processing are defined as process compatibility,
environmentally friendly chemistry,ease of handling,and high yield. According to “voice of the customer”,key dry film
attributes are high resolution,good adhesion to a variety of copper surfaces,good line reproducibility,high yield,and clean
stripping after plating with conventional alkaline solution,that is compatible with existing aqueous waste water treatment.
A novel dry film photoresist for the next generation IC substrate substrates was developed with new polymer technology for
binder polymer and monomer combinations and novel photo initiator systems. This paper covers dry film performance
derived from requirements voiced in the VOC.

This paper describes the performance of several types of the most advanced Dry Film photo Resist (DFR),for producing
high-density package substrates and chip on films (COF).
1) High resolution type DFR,which achieves very fine conductive patterns less than L/S=15/15um by semi-additive plating
process,is discussed.
2) High photosensitive type DFR is presented,which is used for Direct Imaging (DI) exposure systems expected to be
applied to MPU package substrates. In the DI exposure systems,the irradiance of exposure lights affects the DFR resolution.
Selecting a new initiation agents,which has high absorbance at h-line (405nm) for higher photo reaction efficiency,
accomplishes the resolution of L/S=15/15um with 25um DFR thickness. This type of DFR also has high resistance for plating
by using such monomers that increase of photo-reactive groups inside. The current target is L/S=10/10um resolution at quite
low exposure energy,10mJ/cm2.
3) Ultra thin DFR below 5um for high density COF and TAB by subtractive method gives higher performance than
conventional liquid photo resists. The DFR,which has demonstrated excellent 2um resolution and adhesion with 2um
thickness on the experimental basis,extends the application field to near one micron scale,from the previous ten micron
scale.
4) Other grades,thick layer DFR (120um thickness) for electroplating wafer bump formation and DFR for sandblasting
which achieves dry etching of wafers,ceramics and glasses,are also introduced in the paper.

By using two existing pieces of common printed wiring board manufacturing equipment,embedded resistor manufacturers
can obtain laser trim results similar to the trimming obtained using a specialized probe card based laser trimmer. Existing
electrical test equipment can be programmed to first measure the values of plated additive resistors manufactured on circuit
board inner layers. Next,this value information is programmed into the software of a laser routinely used to drill microvias
for circuit boards. A computer routine calculates the amount of the resistor that needs to be removed to adjust each resistor to
the required design value. This trimming is then conducted on the actual inner layer.
Advantages of this technology include eliminating the manufacture of probe cards for each new circuit design,and utilizing
existing machines for this new technology task. While accuracy of trim with this “off line” machine may not be quite as
precise as active trimming with probe cards,the accuracy is sufficient for many of the 5-10% resistor values needed for such
design applications as digital signal termination. Plated additive resistors,with their uniform thickness across each resistor,
are particularly easy for this technology combination to trim.

We have previously published our work on developing thin substrates for use as embedded capacitor layers. Both unfilled
and filled materials were characterized in regards to performance,reliability and manufacturability. It was demonstrated that
higher capacitance density came at the expense of ease of processing.1 A new substrate was developed to address this issue.
As previously shown,high speed digital circuits benefit primarily from the capacitive layers being as thin as possible. For
mobile electronics,however,they want the highest capacitance density so they can remove the most discrete capacitors. With
both these markets in mind,a thin substrate with higher Dk than unfilled systems was developed. A major design objective
was to be able to etch both sides of the substrate at the same time (like traditional power/ground layers).
We will discuss the experiences of PWB shops in processing the material and review the results of the various reliability
studies. Also,test vehicles have been processed for testing at high frequencies to compare against the other capacitive
materials. It will be demonstrated that this new substrate has excellent electrical properties (such as a DK of 10 and the ability
to pass 500 volt High-Pot) while being able to be readily manufactured using typical inner-layer processing.
In addition we have developed a method,which utilizes our highest Dk material,which is compatible with HDI processing.
This process can be used to embed capacitance within an organic chip package.