Nowadays,the growth of electronic industry is remarkable. All electronic devices are getting smaller with higher performance and data
transmission speed. Therefore,we have developed a new profile-free copper foil whose surface roughness (Rz) is less than 1.5 µm with
satisfactory adhesion strength. A new original surface treatment of the profile-free copper foil provided affords good peel strength (0.7
kN/m or more) equivalent to that for the conventional roughened foil with sufficient reliability. With the new profile-free copper foil,the
conventional subtractive method is applicable to the wiring of 60 µm pitch or less,and the short-circuit fault of electroless Ni/Pd/Au
plating,which is prone to occur in fine wiring,will be restrained since the wiring is formed on a smooth surface. Moreover,the
transmission loss at 5 GHz will decrease by 8 dB/m since the surface roughness of the conductor line is suppressed.

Carbon Composite raw material property comparison are summarized below:
-Thermal Conductivity – Watts per meter ? Kelvin.
The core material can spread up to 620.0 W/m?K.
-CTE – parts per million per C.
Carbon Composite Laminate has a very low negative CTE,(-1.10 ppm/C) so it contracts very slightly as temperature rises.
Traditional materials expand considerably as temperature rises. When in plane,the user can tailor the surface CTE of a
standard Printed Circuit Board from 3ppm/C to 12 ppm/C,enabling direct die attach and WLP.
-Density – grams per cubic centimeter.
The material density (and therefore weight) is approximately equivalent to fiberglass. Standard FR4 is 1.85g/cm3 carbon
composite is 1.76-2.20g/cm3. No weight premium.
-Tensile modulus of elasticity – MSI (1,000,000 PSI).
The carbon composite is much more rigid than traditional materials. It is 4 to 10 times the rigidity of standard Fr4. Tensile
modulus is 34-130 MSI per layer depending on raw material selected.
-Dielectric constant – r (relative permittivity).
The relative permittivity of the new material is higher than traditional material,however,it is used only as a plane layer
(preferably ground plane) and is isolated from the copper vias. This material can be drilled through easily so that signals pass
through the carbon composite layer,are isolated,and still can be used throughout the entire board. This eliminates the
concerns of the Dielectric constant of the core material and allows users to simply design the PCB as normal concerning
vias.

This paper presents data collected from a set of electronics manufacturers using an automated optical inspection post-place
system for the purpose of both defect detection and process-control and process monitoring. The data represent a range of
geographical locations (US,Europe,Asia),a variety of different products (cell phones,PC motherboards,etc.),and a long
period of time (seven years). Based on these experimental data,we provide real-life dramatic examples of how analysis of
both attribute and variable data over the short and long term can help increase first-pass yield,keep first-pass yield steady,
and decrease set-up time. These analyses methods can be used in combination with real-time feedback to continuously
improve product quality and,thereby,achieve earlier returns on investment.

With the introduction of Lead-free solder,voiding within BGA joints is potentially a major issue during PCBA manufacture.
With BGA components sometimes costing hundreds or even thousands of US Dollars,there has to be an understanding about
when voiding within the joint is excessive.
There are a number of specifications that a manufacturer can refer to but with respect to BGA joints,IPC-7095A is probably
the most comprehensive. It has an entire section on voiding within the BGA ball and limits on when the void size becomes
either a Process Control issue or a Corrective Action Indicator. However,some of this information seems to conflict with
other IPC specifications,for example IPC-A-610D. Instead of trying to set a global specification,this paper investigates
whether the limits specified within IPC-7095A were acceptable to a particular Contract Manufacturer and their OEM
customer.

Over the last several years there has been a great deal of advancement in post-print inspection technology. The capability to
inspect printed solder paste deposits immediately after the printing process and immediately before the component placement
process has become more accurate,more repeatable and much faster. Post print solder paste inspection systems which are an
integral feature of the printing machine itself or a standalone automated optical inspection (AOI) system are now able to
provide much more reliable inspection capability at or near the speed of the product cycle times.
However,regardless of how sophisticated,no post print inspection system can actually correct the defects it detects. The
existing post print inspection systems can certainly identify the defects and notify the operator or process engineer of a
problem. The identified defect can be fixed before it becomes a more costly defect than if it were discovered later in the
manufacturing process. A process engineer or technician must evaluate the solder paste printing performance data generated
by the post print inspection and/or statistical process control (SPC) systems to determine the “root cause” of the defect and
what action is required to actually eliminate or minimize the problem from reoccurring. No post print inspection system has
ever eliminated any defect from reoccurring without a process engineer implementing permanent corrective action.
The concept of a closed-loop process control solder paste printing process involves a system that not only detects the defects
but also has the intelligence to make adjustment to the process (primarily adjustments to the printing equipment’s operating
parameters) to prevent them from reoccurring. This paper will discuss various concepts of closed-loop process control
involving the solder paste printing process. The discussion includes the current status of our research in this field,benefits,
limitations,the technology required for implementation and future innovations.

Legitimate concern exists regarding sending spacecraft and their associated hardware to solar system bodies where they could
possibly contaminate the body’s surface with terrestrial microorganisms. The NASA approved guidelines for sterilization as
set forth in NPG 8020.12C,which is consistent with the biological contamination control objectives of the Committee on
Space Research (COSPAR),recommends subjecting the spacecraft and its associated hardware to dry heat—a dry heat
regimen that could potentially employ a temperature of 110ºC for up to 200 hours. Such a temperature exposure could prove
detrimental to the spacecraft electronics. The stimulated growth of intermetallic compounds (IMCs) in metallic interconnects
and/or thermal degradation of organic materials composing much of the hardware could take place over a prolonged
temperature regimen. Such detrimental phenomena would almost certainly compromise the integrity and reliability of the
electronics. Investigation of sterilization procedures in the medical field suggests that hydrogen peroxide (H2O2) gas plasma
(HPGP) technology can effectively function as an alternative to heat sterilization,especially for heat-sensitive items.
Treatment with isopropyl alcohol (IPA) in liquid form prior to exposure of the hardware to HPGP should also prove
beneficial. Although IPA is not a sterilant,it is frequently used as a disinfectant because of its bactericidal properties. The
use of IPA in electronics cleaning is widely recognized and has been utilized for many years with no adverse affects reported.
In addition,IPA is the principal ingredient of the test fluid used in ionic contamination testers to assess the amount of ionic
contamination found on the surfaces of printed wiring assemblies. This paper will set forth experimental data confirming the
feasibility of the IPA/H2O2 approach to reach acceptable microbial reduction (MR) levels of spacecraft electronic hardware.
In addition,a proposed process flow in which both IPA liquid and HPGP are utilized will be presented in Section 7.0 Future
Work. A list of acronyms and chemical symbols used throughout this paper is given in Section 9.0 Acronyms and
Chemical Symbols.

Status of thermal cycle test results for a nonfunctional daisy-chained peripheral ceramic column grid array (CCGA) and its
plastic ball grid array (PBGA) version,both having 560 I/Os,were presented in the last year conference. Test results
included environmental data for three different thermal cycle regimes (-55/125°C,-55/100°C,and -50/75°C). The updated
findings for these test vehicles with two different package types will be presented.
In a recent reliability investigation a fully populated CCGA with 717 I/Os was also considered for assembly reliability
evaluation. The functional package is a field programmable gate array that has much higher processing power than its
previous version. This new package is smaller in dimension,has no interposer,and has a thinner column wrapped with
copper for reliability improvement. This paper will also present thermal cycle test results for this package assembly and its
plastic version with 728 I/Os,which were exposed to two different cycle regimes. The cycle profiles were those specified by
IPC-9701A for tin-lead,i.e. -55 to 100°C and -55 to 125°C. Per IPC-9701A,test vehicles were built using daisy chain
package and were continuously monitored. The effects of many process and assembly variables including corner staking,
commonly used for improving resistance to mechanical loading such as drop and vibration loads,were also considered as
part of the test matrix. Optical photomicrographs were taken at various thermal cycle intervals to document damage progress
and behavior. Representative samples of these along with cross-sectional photomicrographs at higher magnification taken by
scanning electron microscopy (SEM) to determine crack propagation and failure analyses for packages are also presented.
Appendix A was added to provide back-up information for IPC-9701A and discuss the effects of key thermal cycle
parameters and projection for lead-free versus lead-based solder joints.

One of the factors that has contributed to the establishment of the Ni-modified Sn-Cu eutectic as one of the major alternatives
to the widely promoted Sn-Ag-Cu alloys as an RoHS compliant lead-free solder has been its apparent fluidity at temperatures
close to its 227°C melting point. This fluidity results in the alloy behaving similarly to lower melting point alloys in which
tin dendrites start to freeze out at temperatures higher than the nominal melting point. This in turn has meant that the Nimodified
Sn-Cu eutectic can be used as a wave solder and a HASL alloy at process temperatures not much higher than those
that have been used with Sn-37Pb solder. More recently it has been found that this fluidity also permits the use of the alloy in
reflow soldering with peak temperatures around 245°C,which is in the middle of the range used with the Sn-Ag-Cu alloys
that have a nominal melting point 10°C lower. In a study reported at APEX 2005 it was found that the Ni addition has the
effect of suppressing the formation of pro-eutectic ß-tin dendrites in the cooling Sn-0.7Cu alloy and promoting solidification
as a true eutectic and it was inferred that it was because of this effect that the alloy exhibited good fluidity close to its melting
point. In the study reported in this paper the fluidity of the modified and unmodified Sn-0.7Cu alloys is compared using two
techniques recognised in solidification science. The Ragone method measures the distance that the molten alloy flows along
a tube,a situation which to some extent simulates through-hole penetration in wave soldering and metallography of the
resulting sample provides a further correlation between the observed behaviour and the resultant microstructure. The
Dendrite Coherency method provides a means of confirming the change in solidification mechanism to heterogenous
nucleation when the Ni is present. The results of these tests are consistent with observed positive effect of the Ni in
enhancing the performance of the Sn-0.7Cu alloy as a practical lead-free solder.

The widespread use of SAC-based (SnAgCu) lead-free solder paste drives the industry toward reflow profiles that are
considerably longer than those used for lead-bearing products. This is due to the narrower process window. The latter is a
result of the higher reflow temperatures on one hand and the limited thermal resistance of the current generation of electronic
components on the other.
The minimized process window requires a significant reduction of ?-T’s between the small and large components. The most
common way to minimize ? -T’s is to extend the soak or ramp before the reflow phase.
It is well understood that the thermal breakdown of most materials is impacted more by prolonged dwell times at higher
temperature levels rather than the temperature level as such. The consequence,for the solder paste,is the thermal breakdown
of the organic material resulting in the loss of the protective flux blanket,finally yielding inferior reflow performance.
Industry sectors that typically have assembly designs with major differences between small and large components have the
option to successfully reflow these assemblies in a Pb-free process with the use of nitrogen to protect the solderability of the
assembly.
Since electronics manufacturing is a cost-driven industry,however,the use of nitrogen is a highly undesirable cost factor.
This paper describes the development and implementation of SAC-base Pb-free solder paste for use in reflow-processes with
extended temperature profiles,but without nitrogen.
It explains the need for flux systems in this generation of solder paste based to incorporate organic materials of longer
molecular chain length. Thermal resistance studies show the advantages of these materials. Also,solutions for the enhancing
the mobility of these materials are provided,impacting the printing properties of SAC-based solder paste.

One of the reported problems in moving to lead free has been increased solder voiding. Current research indicates that paste
formulation,reflow profile and board finish,when selected carefully,can produce equivalent void performance to eutectic
tin/lead systems. A method of simulating solder void conditions under a chip using copper performs is described. These
methods,when combined with traditional BGA porosity testing,are used to study the influences of board finish,paste
formulation,reflow profile and atmosphere on the solder voiding phenomena. All of this work is done with the popular
SAC305 and SAC405 lead free alloys. Finally,there are solutions to lead free solder void formation and one less trade-off in
the global effort to replace lead bearing materials in electronic assembly.