A new bifunctional low molecular weight polyphenylene ether (OPE oligophenylene ether) was obtained by the oxidative coupling of 2,2’,3,3’,5,5’-hexamethyl-[1,1’-biphenyl]-4,4’-diol (HMBP hexamethylbiphenol) and 2,6-dimethylphenol,and several thermosetting resins were synthesized from OPE by changing the end hydroxyl group into other reactive functional groups such as glycidyl ether group(OPE-2Gly) and vinylbenzyl ether group(OPE-2ST). These thermosetting resins keep such superior characteristics of high molecular weight polyphenylene ether(PPE) as low dielectric constant(Dk),low dielectric dissipation factor(Df),high glass transition temperature(Tg) and low water absorption rate,while formability in press and low solubility in organic solvents are desirably to be improved. A cured product of OPE-2ST had Tg :220°C(DMA),Dk(10GHz):2.46,Df(10GHz):0.0020. A curable resin composition containing OPE-2ST and
thermoplastic elastomer such as styrene-butadiene-styrene copolymer (SBS) and hydrogenated styrene-butadiene-styrene copolymer (SEBS) was able to form a curable film by solution casting method. Cured film obtained with aforementioned curable one containing OPE-2ST and SEBS kept high Tg of OPE-2ST because of micro phase separation. Characteristics of the film were Tg:200°C (TMA),Dk (10GHz) :2.29,Df(10GHz) :0.0011. The Df value of this film was close to that of polytetrafluoroethylene (PTFE). These resins are accordingly suitable for printed wiring board (PWB) base materials in
high-speed communication or telecommunication applications.

Increasing operating frequency of IO busses for computing has highlighted the importance of transmission line loss. For FR4 PCB mother boards computing at speeds above 1 GHz this is dominated by dielectric losses. FR4 dielectrics are epoxy based materials which absorb moisture and are subject to dielectric loss variation due to absorption of ambient moisture. Resonator measurements of the substrate alone are useful for modeling but they do not take into account PCB design variables that influence absorption rates. Transmission line loss data and analysis obtained from two PCB designs subjected to a program of drying and moisture absorption are presented. A model to predict absorption rates and transmission line loss is presented. FR4 materials will be compared and contrasted with a low-loss substrate material.

With the enactment of the European Union (EU) ROHS Directive 2002/95/EC (Ref.1),certain electrical and electronic products that are manufactured in or exported to the European Union have restrictions on the use of Lead,Mercury,
Cadmium,Hexavalent Chromium,Polybrominated Biphenyl (PBB) and Polybrominated Diphenyl Ethers (PBDE).
EDXRF (Energy Dispersive X-ray Fluorescence) is one of the methods that can be used for screening of RoHS materials. EDXRF has the advantage of simple or no sample preparation as well as being non-destructive with a relatively short testing
time. However,it has disadvantages such as matrix interference combined with the fact that for most electronic devices,it is difficult or impossible to perform the analysis on homogeneous areas without overlapping other materials on the device. Thus the ‘screening’ results need to be carefully analyzed or verified.
This paper describes the work done on the testing of European Union ROHS 5 of 6 (lead in solder exemption) and ROHS 6 of 6 components and solders with EDXRF equipment (both desktop and handheld). It identifies the various uses and
constraints of EDXRF equipment.

RoHS directives require screening and quantification of certain elements and compounds used in electronics components and parts.
X-ray Fluorescence (XRF) technology has emerged as an effective tool in the screening process of electronic components.
XRF analyzers,bench top and portable,can determine the presence of concerned elements,but not compounds,in a relatively short period of time.
XRF technology is an established analytical method for elemental analyses. However,there are certain technical aspects that directly impact the RoHS application that may require further understanding of XRF principles. The quantitative determination of elements for compliance with RoHS directives could be compromised under certain conditions if the fundamental principles of XRF technology are not well understood and adhered to for this application.
The most influencing factor in XRF application for RoHS compliance is the ability of an XRF system to excite and induce characteristic x-rays of concerned elements without any interference that may result in either false negative or a false positive indication. Any false indication causes operational difficulties and has financial consequences. This factor is more pronounced in electronic components which are often composed of complex matrices and contain elements that could interfere directly with the characteristic x-rays of RoHS-concerned elements.
This paper provides an overview of XRF technology as it is applied to electronic components,the effectiveness and limitations of XRF methods as a screening,and the contributing factors in obtaining accurate measurements.

Environmental compliance is becoming a global effort in the electrical and electronics industry. The Directive on “Restriction of Hazardous Substances” (RoHS) in Europe,is forcing the electronics industry to develop methods for analytical testing of its components and products for regulated substances. The use of lead (Pb),mercury (Hg),cadmium (Cd),hexavalent chromium (Cr VI),and some types of brominated flame retardants (like polybrominated biphenyls,PBB,polybrominated diphenyl ethers,PBDE) in products is being regulated. The industry is convinced of the importance to fulfill this requirement and has looked for confident testing methods to guarantee that banned substances contained in their products are within permitted limits. One of the more suitable analytical methods for the industry to screen and quantify the banned substances is
the Energy Dispersive X-Ray Fluorescence (XRF) because of its nondestructive,fast and result-efficient way of analysis. Analytical techniques are required to make accurate assessments. The purpose of this paper is to discuss how we evaluated the performance of XRF analytical equipment for RoHS application for the five XRF systems including Desktop and Handheld equipment. We use standard samples and production samples for the experiments:
There were four items studied with standard samples with 10,775 readings:
1. Cpk studies with 12 standard samples including PE,PVC,aluminum alloy,brass alloy,and solder alloy types.
2. Gage reproducibility & repeatability.
3. Stability test (five readings/day,and 10 days data collections).
4. Detection level versus acquisition time.
After testing numerous samples,we selected 11 samples with RoHS compliant,non-compliant,and inconclusive compositions to send to two outsourced laboratories. We studied the correlations between XRF and two test laboratories.
With this study,we are confident in the individual XRF capabilities and accurate test levels,capabilities and accurate test levels the individual XRF have. The results provided a good reference for us to review the production sample test results with XRF. The analytical methods will be discussed in the paper.

A perplexing challenge for RoHS compliance is adapting large,complex and thick,high-layer count multilayers to lead-free assembly. These are typically dense,complex assemblies with large BGAs and significant heat spreading features integrated into the design. Fine-pitch packages (QFPs and BGAs) and increasing pin count of packages further complicates the conversion to RoHS.
To provide RoHS robustness to an assembled multilayer that has a very high heat-sinking characteristic requires that the total layers be reduced,as well as its overall thickness. But how can this be accomplished? The answer is to increase signal routings per layer by 2X to 4X,and thus reduce overall signal layers and their referenced plane layers. The other new design feature is to change ‘topology’ so that a majority of vias are now ‘blind vias’,thus freeing up innerlayer space for this to be accomplished. HDI is the interconnect technology that has been developed to respond to these needs. Microvias are the principal feature of HDI,along with thinner dielectrics and smaller traces and spaces. The important feature is the “Design For Lower Layers Using HDI”. This paper covers the major design solutions from HDI that allows designers to implement fewer layers in a multilayer:
• Reduction in layer count for thickness control and RoHS compliance (Lead-Free Assembly)
• How to integrate high-I/O and fine-pitch devices without adding layers
• How to achieve higher component density and component I/Os without adding layers The resulting new multilayers are not only thinner and easier to design but are less expensive and suitable for lead-free
assembly. The resulting new multilayers are not only thinner,cheaper,and easier to design but are less costly and suitable for lead-free assembly.

With design requirements becoming more stringent as implementation of new technology standards evolve,designers are faced with the challenge of front-loading more effort in the design cycle than ever before. The need for simulation in all facets of the product design,whether the Engineer is in the middle of drawing his schematic or a layout designer is in the middle of routing his printed circuit board,has become common.
This introduces a new design task where an Engineer has to hunt for device models or does various what-if analyses to test out the termination scheme or to manage DDR2 functionality within their signal integrity tools. Setting up differential pair drivers and testing them versus multiple layer stack-ups based on a chip maker’s requirements and takes time and effort,and we all know that in most cases,the “time” aspect is relatively scarce. To help in the effort to enhance predictability and turnaround time,a simulation kit can be used as part of the design process.

The routing of large pin-count and dense BGAs has a significant impact on the cost of the PCB,primarily in terms of layer count and via technology. This paper is the result of considerable research done with the intent of providing a general flow solution to the BGA breakout problem. It explores the need for collaboration between chip,package and PCB designers - emphasizing the dependencies that need to be managed to reduce board costs. The number of variables confronted in large BGA routing is significant and this paper reveals solutions based on a logical analysis of ASIC and FPGA BGA pin density,array patterns,packaging requirements,pin swap constraints,layers,via technology,topology planning and routing methods.

The Quad Flat No-Lead or QFN packages are increasing in their utilization in the printed circuit board market. This is being driven largely by the shrinking size both in profile and footprint,higher operating speeds from 2 GHz to 10 GHz,effective thermal dissipation all in a low cost package. The relatively inexpensive nature of leadframe-based CSPs (chip scale packages) such as QFN’s without solder balls has led to the popularity of these devices being utilized in commercial
electronics. TechSearch International reported that there was an increase in the utilization of these devices in subcontractors from 77% to 85% from 2004 to 2005.1 Another example of the increase in utilization,focused in Japan,is that for portable consumer products such as digital video cameras the QFN was found in 5% of applications in 2004 and is predicted to be at 10% in 2014.1,2 Even package vendors such as Amkor Technologies now advertise that they have sold over 1 billion QFN packages.3 As QFN usage grows,they will eventually replace the currently dominate format,fine-pitch gullwing & quad flat IC package,
As with the increase in any type of joint usage,there is an increase in the opportunity for defects. Currently,only generic test requirements for the QFN exist in the industry. Like area array grid packages,the QFN solder joint is below the joint,hidden from most types of optical inspection test. X-ray inspection provides an effective solution in testing these types of joints.

As printed circuit board assembly (PCBA) becomes more complex,Automatic Optical Inspection (AOI) and Automatic Xray Inspection (AXI) systems are becoming more widely used in electronics manufacturing. AXI has good defect detection capabilities,but its TaKT time becomes a concern when compared to other machines (screen printer,pick-and-place,reflow,and wave soldering) on the SMT line. How can these two testing machines be used effectively to test production? This translates into: (1) how can we reduce AXI test time by supplementing it with AOI? And (2) how can we use the AOI and
AXI test results to improve the overall manufacturing process and thereby increase production yields? Some studies were reported in the past with only AXI1-3. We have been doing this project with AOI and AXI test data analysis to improve assembly test yields.
With the Flextronics Manufacturing System (FMS) approach,we focus on Lean Manufacturing. Lean is a manufacturing philosophy that recognizes WASTE as the primary driver of cycle time,and employs techniques to continually drive out
waste in the various processes. Waste elimination is the most effective means to achieve cycle time reduction. We develop new processes to deal with three types of waste: (1) Over process (2) Defect waste,& (3) Inventory accumulation. We used the key elements of Six Sigma DMAIC (Define,Measure,Analyze,Improve,& Control) and statistical tools for the project. In this study we first started with one customer’s product,which previously had 100% components covered with AOI and >95% covered by AXI. We studied AOI,AXI,ICT,and Functional Test data for six months,and reduced AXI test coverage for some non-critical components. As a result of the reduction of AXI coverage,we were able to reduce AXI test time from above 4 minutes to below 3 minutes. In the meantime we also focused on process issues and improvements using daily AOI
and AXI test results. Test and process engineers worked together on this project and used the AOI/AXI test results to adjust the machine settings for solder paste printing,pick and place,and wave soldering machines; solving the process and material issues and making very good progress. An example of one product: We reduced AXI test time by only testing BGA,Fine Pitch ICs,RNs,and some “Critical to Function” parts. Therefore AXI component and pin coverage changed from 98.4%,and 98.9% to 13.6%,50.1% respectively. AXI test time was reduced from 4.1 minutes to 2 minutes. Meanwhile,the yields of AOI (top),AOI (bottom),AXI,ICT,and FT increased from 98.9%,97.3%,88.4%,98.9%,and 100% to 99.6%,99.0%,96.2%,98.9%,and 100% respectively. The cost saving results will be discussed in the paper.