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The Effect of Ni on the Microstructure and Behaviour of the Sn-Cu Eutectic Lead-free Solder

While the Ni-stabilized Sn-0.7Cu alloy is now well established as a viable lead-free solder in large scale commercial printed circuit board assembly the effect of Ni is not yet fully understood .. read more
Author(s)
Keith Sweatman,Tetsuro Nishimura
Event
IPC APEX EXPO 2005

Lead Free Flip Chip and Chip Scale Package Inspection: New Challenges Will Require New Inspection Technologies

Lead free implementation will present new challenges for PCB manufacturers from a design,soldering process,and QC standpoint. The higher reflow process temperatures will cause greater thermal s .. read more
Author(s)
Mark Cannon,Juergen Friedrich
Event
IPC APEX EXPO 2005

OEE,the New Gauge on the Dashboard for the PCB Assembly Industry

OEE (Overall Equipment Effectiveness) is commonly used in a wide range of businesses when it comes to measuring and monitoring manufacturing performance. Even though OEE has been applied in var .. read more
Author(s)
Henning Mærkedahl
Event
IPC APEX EXPO 2005

An Open Standards Based Approach to the Exchange of Data in an Automated Electronics Assembly Operation

A tier one supplier to the automotive industry has determined that a key to staying competitive in the electronics manufacturing industry is to adopt open standards for the exchange of data. Sp .. read more
Author(s)
Louis Watson
Event
IPC APEX EXPO 2005

Optimizing Production Cost with Electronic Manufacturing Simulation

Factory simulation has been used extensively to optimize and reduce costs across many manufacturing disciplines. Unfortunately,general purpose factory simulators do not effectively model the sp .. read more
Author(s)
Chet Palesko
Event
IPC APEX EXPO 2005

Filling Pastes in PCB Production – Fields of Application,Possibilities and Limitations

In the past the use of filling pastes in PCB production was largely limited to via hole fillers. These materials with a solids content of 100% are still successfully employed today to close via .. read more
Author(s)
Sven E. Kramer
Event
IPC APEX EXPO 2005

The Feasibility of Blind Via on PTFE-FR4 Laminated Multi-Layer PCB

PTFE-FR4 hybrid laminated multi-layer PCB technology is being applied more and more widely. This technology requires blind via fabrication in a PTFE core. This paper gives a picture of the manu .. read more
Author(s)
Kong Lingwen
Event
IPC APEX EXPO 2005

Backdrilling Technology for Backpanel

In order to get excellent signal Integrity,half PTH holes will be a new trend in high frequency backpanel designing. Backdrilling is necessary for this application. This paper explores the appl .. read more
Author(s)
Zeng Ping,Kong Lingwen
Event
IPC APEX EXPO 2005

Direct Immersion Gold as a Final Finish

In this study,the DIG process (Direct Immersion Gold),is investigated. DIG is a process in which gold is plated directly on copper as a surface finish for printed circuit board and package appl .. read more
Author(s)
Shigeo Hashimoto,Masayuki Kiso,Yukinori Oda,Horshi Otake,George Milad,Don Gudaczauskas
Event
IPC APEX EXPO 2005

Characterization,Reproduction,and Resolution of Solder Joint Microvoiding

Microvoids are tiny voids in solder joints and differ from the more well known solder joint voiding in their individual size and location. The microvoids discussed herein are described as an ab .. read more
Author(s)
Donald P. Cullen
Event
IPC APEX EXPO 2005

Implementing Laser Marking of Printed Circuit Boards

Manufacturers of electronic devices,from home audio equipment to automotive keyless entry systems,are increasingly seeking a reliable,cost effective method for uniquely identifying and tracking .. read more
Author(s)
Rick Stevenson
Event
IPC APEX EXPO 2005

Conductive Polymer Imaging For Communications and Electronics

Conductive inks and polymers based on metals were originally envisaged for quick repairs to Printed Circuit Boards (PCBs) and semiconductor chips. Increasingly these materials are being used to .. read more
Author(s)
Richard Mosses
Event
IPC APEX EXPO 2005

Optimization of Lead-Free Soldering Processes for Volume Manufacturing

In this paper,a comprehensive review is provided on the optimization of soldering processes (including reflow,wave soldering,and rework),for different component types,different PCB sizes and fi .. read more
Author(s)
Dongkai Shangguan
Event
IPC APEX EXPO 2005

Lead-Free Solder Flip Chips on FR-4 Substrates with Different Assembly Processes and Materials

This study is focused on using different assembly options such as dip fluxing,flux jetting and reflow encapsulate for 200- 250um pitch lead-free (SnAgCu) flip chips on FR4 substrates. The impac .. read more
Author(s)
David Geiger,Dongkai Shangguan,Jonas Sjöberg,Todd Castello
Event
IPC APEX EXPO 2005

New Concept Multi-Layer FPC “SBic” For High-Density Device Mounting

We have developed a thin,high-density device-mounting,multilayer flexible printed circuit (hereinafter flexible printed circuit is referred to as FPC) “SBic” (stands for Solder Bump Interconnec .. read more
Author(s)
Toshiaki Chuma,Toshio Komiyatani,Mikihiko Ishibashi
Event
IPC APEX EXPO 2005

Flexible PCB Plating Through Hole Considerations,Experiences and Solutions

Due to the worldwide increase in demand for flex and flex-rigid panels as well as the shift in the required designs of panels there is an extreme need for improved PTH processing. There are sev .. read more
Author(s)
Neil Patton
Event
IPC APEX EXPO 2005

Environmentally Friendly Low Transmission Loss Base/Multilayer Materials

The frequencies used to communicate and process information have been extended beyond the GHz band to the microwave band to handle the growing volume of data. Moreover,increasing global interes .. read more
Author(s)
Hiroshi Shimizu,Kenichi Tomioka,Shinji Tsutikawa,Nobuyuki Minami,Yasuhiro Murai
Event
IPC APEX EXPO 2005

Novel Material having Low Transmission Loss and Low Thermal Expansion designed for High Frequency Multi-layer Printed Circuit Board Applications

A new multi-layer PCB (printed circuit board) having low transmission loss and low thermal expansion that meets up-coming further high speed and high volume data transmission demands was develo .. read more
Author(s)
Hiroaki Fujiwara,Hiroharu Inoue,Shoji Hashimoto,Mitsuhiro Nishino,Kiyotaka Komori and Tatuo Yonemoto
Event
IPC APEX EXPO 2005

Semiconductor Technology ITRS Roadmap

For four decades,the semiconductor industry has distinguished itself by the rapid pace of improvement in its products. The principal categories of improvement trends are shown in Table 1 with e .. read more
Author(s)
Alan Allan
Event
IPC APEX EXPO 2005

System in Package: Identified Technology Needs from the 2994 iNEMI Roadmap

System in package (SiP) technology has grown significantly in the past several years. It was barely mentioned in the National Electronics Manufacturing Initiative’s (NEMI’s) 2000 roadmap,but by .. read more
Author(s)
James Mark Bird
Event
IPC APEX EXPO 2005

Roadmap to Compliance: The Role of Electronic Data Exchange in Supporting the European Union RoHS and WEEE Directives

The upcoming European Union RoHS and WEEE directives are driving new requirements for the management and exchange of information,both across the extended electronics manufacturing value chain,a .. read more
Author(s)
Richard Kubin
Event
IPC APEX EXPO 2005

Site-Specific Measurement of Cathodic Pulse Shape and Plating Current Density for Optimization of Pulse Plating Lines

Two important aspects concerning optimum performance of a (reverse) pulse plating line are (i) the uniform and correct pulse shapes anywhere on the PCB and (ii) the uniformity of the plating cu .. read more
Author(s)
Detlev Nitsche,Stefan Gerhold,Nasser Kanani
Event
IPC APEX EXPO 2005

The Property Research and Applications of Vertical Pulse Copper Plating

Horizontal and vertical pulse plating have been widely used for panel plating in PCB industry,but rarely used for pattern plating. This article analyzes and reviews the crystal structure,throwi .. read more
Author(s)
Su Peitao,Su Zhangsi
Event
IPC APEX EXPO 2005

A Performance Simulation Tool for Bipolar Pulsed PCB Plating

The copper plating process is one of the most critical steps in the high end PCB manufacturing process. Although the deposition inside through holes and blind holes is the key factor for reduci .. read more
Author(s)
Gert Nelissen; Bart Van den Bossche,Luc Wanten
Event
IPC APEX EXPO 2005

Understanding the Impact of Accelerated Temperature Profiles on Lead-Free Soldering

Traditional reflow profiles for lead-free soldering typically require longer processing times due to elevated peak temperatures and flux activation times defined by solder paste suppliers. Thes .. read more
Author(s)
John L. Evans,Julius Martin,Charles Mitchell,Bjorn Dahle
Event
IPC APEX EXPO 2005

Maximizing Lead Free Wetting

As lead free assembly is ramping up,wetting of lead free solder pastes is surfacing as the major paste performance tradeoff. Global efforts to significantly increase lead free wetting chemicall .. read more
Author(s)
Richard Lathrop
Event
IPC APEX EXPO 2005

Effects of Cooling Slopes in Lead Free Reflow

As more electronic assemblers move to lead free SMT production,concerns are raised over reflow cooling slopes and effects on solder joints. Due to the higher peak temperatures,cooling slopes ar .. read more
Author(s)
Effects of Cooling Slopes in Lead Free Reflow
Event
IPC APEX EXPO 2005

Reliability and Requirement of HDI Blind Hole

Nowadays there are two major ways to achieve the conducting function of HDI Blind Hole One is to employ conducting metal paste to fill in the blind holes after laser drilling. The other is to f .. read more
Author(s)
Ma Zhibin,Ye Liting
Event
IPC APEX EXPO 2005

New Circuit Formation Technology for High Density PWB

To meet future requirements for PWBs,various technologies of processes,materials and tools of PWBs have been discussed. Especially important are technologies of circuit formation for high-end P .. read more
Author(s)
Ryoichi Watanabe and Hong Won Kim
Event
IPC APEX EXPO 2005

Internal Strain Free & Homogeneous Glass Fabrics for High Performance HDI Boards

A recent trend of increasing circuit density,particularly in the areas of plastic packages and multi-layer boards,has resulted in ceaseless demand of improved mechanical properties for laminate .. read more
Author(s)
Shinji Yoshikawa,Yoshinori Gondoh,Yasuyuki Kimura
Event
IPC APEX EXPO 2005

20μm Prepreg Substrates for Ultra-Thin Insulated Single-Layer

Recent increasing demand for miniaturization and multi-functionality of electronic devices has lead to higher PWBs circuit density design,requiring thinner insulation layers,smaller via holes a .. read more
Author(s)
Shinichiro Tachibana,Daisuke Matsude,Yasuyuki Kimura
Event
IPC APEX EXPO 2005

Development of the High Thermal Conduction Laminates for Large Current Board

With the objective of developing high thermal conductive laminates capable of being used as high current-carrying wiring boards for automotive and industrial applications,we identified the opti .. read more
Author(s)
M. Ito,H. Yamanaka,M. Hattori,Y. Takahashi,Jun Kanai,M. Yonekura,M. Kamata,K. Fukushima,H. Takahashi,Y. Takezawa
Event
IPC APEX EXPO 2005

Japan’s JISSO Technology Roadmaps

Japan has a long history of publishing very important technology roadmaps. Some of the Japanese roadmaps published in the past are: JPCA Roadmaps Report on the Technology Roadmap for Advanced S .. read more
Author(s)
Henry H. Utsunomiya
Event
IPC APEX EXPO 2005

The European Roadmap

A unified European roadmap for PWBs does not exist today. It is also most unlikely that a unified roadmap will available in a foreseeable future time. However,the EIPC has worked together with .. read more
Author(s)
Michael Weinhold
Event
IPC APEX EXPO 2005

What makes the IPC Roadmap Unique?

Have you ever been confused after you have read two or three different roadmaps and even though they were supposedly mapping the same attribute in the same time periods,the numbers in the cells .. read more
Author(s)
John T. Fisher
Event
IPC APEX EXPO 2005

Characterization of Acid Copper Plating Solution for Via-Filling

The use of acid copper plating process for via-filling effectively forms interlayer connection in build-up PWBs with high-density interconnections. However,in the case of copper film deposited .. read more
Author(s)
Hideki Hagiwara,Hideo Homma,Ryoichi Kimizuka
Event
IPC APEX EXPO 2005

Improving Printed Circuit Board Plating with Eductor Agitation

This paper will review eductor agitation systems at PWB installations to improve the electroplating of printed circuit boards. Significant environmental and productivity improvements have been .. read more
Author(s)
Charles Schultz
Event
IPC APEX EXPO 2005

'Bridging the Gap’ – Technical Capabilities of a Direct Plate PTH Process

In contrast to electroless copper,direct metallization processes are inherently less expensive to operate,more environmental friendly,requires less floor space and are more efficient. Among the .. read more
Author(s)
Richard Retallick,Hyunjung Lee,Ying (Judy) Ding,Timothy Spencer
Event
IPC APEX EXPO 2005

Perspectives on Repaired Lead-Free Solder Joints

The use of lead-free (LF) solders as a replacement for traditional tin-lead (SnPb) solders in military and high reliability applications has a number of technical challenges unique to the indus .. read more
Author(s)
Richard Colfax,Matthew O’Keefe,Patricia Amick,David Kleine,Steve Vetter,Dale Murry
Event
IPC APEX EXPO 2005

The Use of SAC Solder and Pb-Free Lead Materials in the Repair Scenario

Much work has been done involving the introduction of RoHS and WEEE Directives across the European Union and the world. Although the use of Pb is limited in new products and equipment,older Pb- .. read more
Author(s)
Mark Woolley,Jae Choi
Event
IPC APEX EXPO 2005

Corrosion Factor and Effects of Tin - Zinc Lead-Free Solder on Copper Substrate in Environmental Tests

We coated copper substrate with tin-zinc lead-free solder (Sn-9Zn and Sn-8Zn-3Bi),and then we performed the following corrosion tests: the salt mist test,the gas corrosion test,and the weatheri .. read more
Author(s)
Hirokazu Tanaka
Event
IPC APEX EXPO 2005

Next Generation High Density Build-Up PKG Substrate

In recent years,along with the further progress of network systems,mobile communication systems and high performance servers printed wiring boards (PWBs),which are key components in these produ .. read more
Author(s)
Takashi Shuto,Kenji Takano,Kazuya Arai,Munekazu Shibata,Junichi Kanai,Kaoru Sugimoto
Event
IPC APEX EXPO 2005

Qualification of ALIVH-G Boards for Handset Assembly

The trends of increased functionality and reduced size of portable wireless products,such as handsets; PDAs are demanding increased routing densities for printed circuit boards. The handheld wi .. read more
Author(s)
Mumtaz Y. Bora
Event
IPC APEX EXPO 2005

Use of Novel Adhesive-lined CCL Material in Single-pressed Multi-layer Circuit Boards with Inner Via-Holes in all Layers

This newly developed material and process enable the manufacturing,using a single pressing process,of multi-layer circuit boards with inner via-holes in every layer. Because this material utili .. read more
Author(s)
Daisuke Kanaya,Shuji Maeda,Keiko Kashihara,Kenji Ogasawara
Event
IPC APEX EXPO 2005

New Improved Polyimides for Increased Reliability

A Design of Experiment (DOE) was conducted to determine the best filler,or combination of fillers that would offer the best reduction of CTE expansion from 50oC to 260o C without compromising e .. read more
Author(s)
David Bedner,Gayle Baker,William Varnell
Event
IPC APEX EXPO 2005

All Polyimide Thin Multi-Layer Substrate

As a promising candidate for future substrate with high pin-count and low transmission loss at high frequency,we have developed an all polyimide multi-layered board laminated by single batch pr .. read more
Author(s)
Shoji Ito,Dr. Shoichi Takenaka,Takaharu Hondo,Masahiro Okamoto,Osamu Nakao
Event
IPC APEX EXPO 2005

Novel Polyimide Build-up Material for Fine-line Fabrication

We have developed a new thermosetting polyimide build-up material for high performance build-up PWBs,which can mount high speed CPUs with high I/O numbers. These PWBs meet the following require .. read more
Author(s)
Takashi Itoh,Shigeru Tanaka,Kanji Shimoosako,Masaru Nishinaka,Mutsuaki Murakami
Event
IPC APEX EXPO 2005

Design of Experiment in Micro-Via Thermal Fatigue Test

The objectives of the present study are to design,fabricate,and test various configurations of micro-vias over military thermal environment,and then evaluate the impacts of micro-via design/man .. read more
Author(s)
T. E. Wong,H. S. Fenger,I. C. Chen
Event
IPC APEX EXPO 2004

Qualification of Stacked Microvia Boards for Handset Assembly

The trends of increased functionality and reduced size of portable wireless products,such as handsets and PDAs,are demanding increased routing densities for printed circuit boards. The handheld .. read more
Author(s)
Mumtaz Y. Bora
Event
IPC APEX EXPO 2004

Evaluation of Underfill Material on Board Level Reliability Improvement of Wafer Level CSP Component

In recent years,Wafer Level Chip Scale Packages (WLCSP) are used not only in the hand held devices but also in high-end networking and telecommunication products. Due to their small footprint a .. read more
Author(s)
A.C. Shiah,Tom Liu,Ken Lee,Y.S. Chen,C.S. Wang
Event
IPC APEX EXPO 2004