Pick-and-Place Feeder density within SMT and Electronics Assembly

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With the growth of Surface Mount Technology (SMT) driven by new technological innovations and next generation products, machine feeder density becomes extremely important in electronics manufacturing. 

As products become more intelligent, diverse and efficient, the associated product BOM (Bill of Materials) and parts diversity increases in scope. This increase in parts count and diversity per product drives the necessity for higher feeder density per Pick-and-Place (P&P) machine.

This per machine feeder density also becomes critical when constructing and accurately determining the potential SMT production lines to fulfill customer needs without resulting in an excess or ‘over capacity’ situation. Constructing a SMT production line based on the requirement of feeder input vs. CPH (components per hour) increases the capital equipment cost of the P&P segment of the line. With a larger percentage of the P&P equipment cost associated to CPH rather than the amount of feeder inputs available at the machine level, in essence end users pay more for CPH vs. feeder inputs. With current and future consumer demands for ever increasing product intelligence this creates an under achieving or underutilized capacity production line for manufacturers.

A balance between machine feeder inputs needed for product diversity and CPH to meet customer required volumes is essential for the highest efficiency production lines.  One way to increase the feeder machine density is to utilize the thinnest feeder possible or to combine feeder positions, forexample, 2 for 1 or 2 for 3. A disadvantage of a combined feeder input solution is reduced ease of use and flexibility. Utilizing a single input feeder increases ease of use and adds the highest level of flexibility to accommodate the most diverse products now and in the future.

Feeder per machine density can be measured in 2 ways, either by total amount of 8mm inputs per linear meter or total amount of 8mm inputs per m². Of course a higher number results in higher production flexibility to address product diversity without creating an over capacity production line.

In order to keep up with the fast moving consumer products technology and diversity, P&P machine suppliers must increase feeder density in traditional ways or by means of new creative innovations to better serve the end user.

Author(s)
Terry York
Resource Type
Technical Paper
Event
IPC APEX EXPO 2020

Impact of PCB Manufacturing, Design, and Material to PCB Warpage

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Customer demands for smaller form factor electronic devices are driving the use of thinner electronic components and thinner printed circuit boards (PCB) in the assembly process. The use of thinner components and thinner multi-up panel PCBs (≤ 1 mm) has led to PCB warpage issues in the surface mount (SMT) assembly process, which in turn impacts the PCB assembly yield. PCBs with excessive warpage impact paste print quality in the print process, and solder joint formation during reflow soldering leading to SMT assembly defects. Lack of industry standard for PCB warpage at reflow temperature further compounds the PCB warpage risk to SMT assembly yield. This paper will use high temperature warpage metrology to evaluate the impact that PCB manufacturing, design, and material has on ball grid arrays (BGA) and panel area PCB warpage by varying the PCB post processing (Bake vs. No-Bake), panel location (corner vs. center), PCB thickness (0.8 mm vs. 0.6 mm), Material (Mid Tg vs. High Tg), and processing (i.e. lamination at condition A vs. B).

Author(s)
Antonio Caputo
Resource Type
Technical Paper
Event
IPC APEX EXPO 2020

California Proposition 65 Review

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Warning required to be provided for exposing person to a listed chemical, unless “person in the course of doing business” can demonstrate it does not pose “significant risk”   •Approximately 900 listed chemicals  •75+% involve lead and phthalates

Author(s)
Michael Easter
Resource Type
Slide Show
Event
IPC APEX EXPO 2020

Update on Proposition 65

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California

Clear and reasonable warnings

•Overview of new warning regulation  •Retailer warnings accompanying sale  •Warnings website •Listings•Compliance assistance  •Safe Harbors  •Safe Use Determinations and Interpretive Guidance

Author(s)
Carol Monahan Cummings
Resource Type
Slide Show
Event
IPC APEX EXPO 2020

Pb-free BGAs in a SnPb Assembly: An Overview of ARP6415

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Intended for use as technical guidance by ADHP (Aerospace, Defense, and High-Performance) electronics system customers to provide the technical structure needed to allow the designer to evaluate the options for using Pbfree BGAs in an assembly that has not converted to full Pb-free assembly

Author(s)
Ben Gumpert
Resource Type
Slide Show
Event
IPC APEX EXPO 2020

Qualified Manufacturing Process Development by Applying IPC J-STD-001G Cleanliness Standard

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J-STD-001G Amendment 1 standard requires an OEM and EMS to qualify soldering and/or cleaning processes that result in acceptable levels of flux and other residues. Objective evidence shall be available for review. The use of the historical 1.56 μg/NaCl equivalence/cm2value for ROSE, with no other supporting objective evidence, is not considered acceptable for qualifying a manufacturing process.

The core concept for materials compatibility and residue acceptability is that of the qualified manufacturing process (QMP). In a QMP, manufacturing materials and processes used to qualify and validate production hardware confirm electrical performance in hot/humid conditions. The purpose of this research is to apply the methods documented in the standard to qualify and validate acceptable levels of flux and other residues when implementing a change in cleaning material and cleaning machine.

Author(s)
Mike Bixenman
Resource Type
Technical Paper
Event
IPC APEX EXPO 2020

Transient AMR Project for Semiconductor Products: Phase 1

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Findings and recommendations are reported from phase 1 of the Transient AMR(absolute maximum ratings) project, which is sponsored by the EOS/ESD Association and Industry Council on ESD Targets, and DfR Solutions. The project includes an industrywide survey about how AMRs of semiconductor products are determined and interpreted. Semiconductor manufacturers design the products to be reliable, as long as AMRs are never exceeded. Electronic system customers continue to increase their reliability expectations, especially in markets such as automotive. This project is of great importance to the electronics industry because customer returns of semiconductor parts continue to indicate that they have been overstressed, suffering electrically induced physical damage (EIPD). Transient excursions above AMR account for many failed parts, but root causes are difficult to discover as they happen unexpectedly, rendering the units unreliable. Manufacturers must ensure that published AMRs are clear and complete. Semiconductor customers and board and system designers must be educated to properly interpret AMRs on datasheets so they can take appropriate action to preserve the built-in reliability of semiconductor parts.

Project work is carried out at DfR Solutions, with some assistance by Industry Council representatives. Survey and literature search results will be summarized, including current practices regarding the determination, reporting, and interpretation of datasheet AMRs. Recommended best practices will be discussed. Case study examples from various companies will be shared anonymously.

Author(s)
Stevan Hunter
Resource Type
Technical Paper
Event
IPC APEX EXPO 2020

Measuring the Impact of Test Methodsfor High-Frequency Circuit Materials

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High-frequency materials are characterized by several important parameters, including the dielectric constant or relative permittivity (εr) and the dissipation factor (Df). For those parameters to have meaning for circuit designers, they must be measured using methods that deliver accurate, repeatable results. However, circuit materials are characterized by many different test methods: For measuring εr, IPC has 12 different test methods.  Many other organizations, including ANSI and IEEE, have their own test standards for characterizing εr.Each measurement method provides detailed insights into the properties of the material it is testing, and the results of each test method may be correct, but they also may not agree. What follows is a review of different methods for measuring εralong with useful modifications and even some suggestions for new Dk measurement approaches.

Author(s)
John Coonrod
Resource Type
Technical Paper
Event
IPC APEX EXPO 2020

A Cost-Effective Method for Accurate PCB Impedance Simulation of Any Specific Stack-Ups

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This paper analyzes the reasons of inaccurate PCB impedance simulation of the traditional simulator and introduces a novel and cost-effective method for accurate PCB impedance simulation of any specific stack-ups. The new method doesn't need to extract material properties from prototype boards or empirical modified DK from PCB Fabs. The test results show the new method & tool have better precision simulation ability with deviation less than 2.5%, compared with traditional simulation tool. It can meet the requirement of less than 5% tolerance impedance to match the high speed & high frequency PCB design, and consequently leads to a more cost-saving and time-saving method to rapidly occupy the market.

Author(s)
Terry Ho
Resource Type
Technical Paper
Event
IPC APEX EXPO 2020