New product introduction at an Original Equipment Manufacturer (OEM) typically includes reliability testing in the form of thermal cycling. Samplings from the engineering models of a new product line were consistently failing the optical testing following the reliability testing. Cross sectioning revealed stress fractures in the solder joints of the LGA ceramic image sensor component. As the image sensor dominates one side of the PCA, the root cause appeared to be Coefficient of Thermal Expansion (CTE) mismatch between the FR4 material of the PCA and the ceramic body of the image sensor. As this new product line was to be high volume, the goal was to avoid introducing an additional component under fill process step and resolve reliability issues through basic SMT assembly processes at the Contract Manufacturer (CM).

A joint OEM-CM Tiger Team explored the contributions of both the solder paste volume and the reflow temperature profile to the robustness of the LGA solder joints. The stencil design aspect included the shape of the aperture and the resulting volume of solder paste deposited. The solder paste volume affects the standoff of the component from the PCA. The sensor manufacturer datasheet for the oven reflow profile allowed a range of temperature values, the most significant being the temperature cool down slope. The cool down slope affects the granularity of the solder joint. The CM’s team performed a DOE maximizing and minimizing both the solder paste volume and the temperature profile cool down slope combinations.

The DOE results trended towards higher paste volume and steeper temperature cool down slope. The risk of solder bridging using the higher paste volume was minimal, but the steeper temperature cool down slope produced unacceptable process voids. Therefore, the choice for optimal SMT process condition was a combination of high solder volume and lower temperature cool down slope. Passing results for optical testing post reliability testing, followed by cross section, validated this optimization. Introduction Reliability testing performed as part of new product introduction included thermal cycling to simulate long-term reliability of the soldering. For this product, the temperature range was -40°C to 85°C, with a cycle consisting of 15 minutes at low temperature, 5°C/minute rise for 25 minutes, 15 minutes at high temperature, 5°C/minute fall for 25 minutes, and repeated for 300 cycles. This testing simulates reliability for 8.6 years based on IPC-SM-785 and IEC 60068-2-14. The product was not powered during the thermal cycling. Following the reliability test, the product’s image sensor underwent optical testing. A significant number of the test samples failed.

In automotive applications, electronic products are subject to several loads, among which thermomechanical loads are particularly affecting the product reliability. Temperature cycling tests on free PCB aim to reproduce the thermal mismatch load at solder joint level, based on coefficients of thermal expansion but does not take into account the real mechanical load applied in the product. The latter, influenced by design elements like housing or screws, has to be determined separately for each product. The new proposed approach enables electronic component design for reliability by developing an experimental and simulation test method combining products relevant thermal mismatch and mechanical loads. For this, PCBs undergo an experimental bending test under temperature cycling. For each tested component and each mechanical load level, a lifetime loss-factor is determined. The influence of component positioning on PCB, i.e. orientation is also considered. Experimental bending test results are then combined with detailed simulation models for complex components, i.e. BGA, to establish Wöhler-like curves and lifetime models. The transfer of those generated models into relevant electronic products enables reliability prediction i.e. layout design. Moreover, bending test combined to temperature cycling allows the visualization of potential failure mode changes at high bending levels (i.e. IMC cracks). This is an advantage versus free PCB test to avoid field and test failures on product level by early detection of bending sensitive components. At long-term, this new method aims to reduce the experimental costs by using the generated lifetime models for further reliability predictions.

This paper presents assembly challenges and reliability evaluation by thermal cycling for a 2.5D [aka, System in Package (SiP)]in a fine pitch ball grid array (FPBGA). More importantly, it presents the effect of underfilling of the top CSPs assembled on to interposer on the overall SiP reliability behavior.  A large number of variables were considered in the design of experiment including evaluation of bare FPBGA without parts on interposer, FPBGA balls either with SAC305 or SnPb solders, FPBGA fully/partially populated with CSPs and flip chip (FC) die on FPBGA interposers, and CSPs with and without underfills on the SiP interposer. 
Assembly of mixed SiP packages becomes a challenging task and required to be characterized by X-ray for solder-joint quality and by Shadow Moiré analysis for warpage characterization. Acceptable assemblies with and without underfilling CSPs on interposers were then subjected to thermal cycling between–40C and 125C for reliability evaluation and failure-mechanisms assessment. Details of design, characterization by X-ray and Moiré,  as well as reliability behavior of the SiP FPBGA due to thermal cycling exposures are presented. Failure analysis results also presented covering evaluation by optical, scanning electron microscopy (SEM), X-sectioning, and dye-and-pry evaluation. The Weibull plots of cycles to failures for SiP FPBGA with SAC305 and SnPb balls and CSP assemblies with and without underfills were presented. Finally, generic discussions were presented on the positive and negative effects of underfills at assembly level and specific reasons for early failures of SiP FPBGAs with CSPs assembled on to interposer with underfill.

KEY WORDS: SiP, system in package, 2.5D, Ball grid array, fine pitch BGA, FPBGA, solder joint reliability, underfill, thermal cycle, thermal shock cycle, Moiré, dye-and-pry

Polymer Thick Film(PTF)-based printed electronics (aka Printed Electronics) has improved in durability over the last few decades and is now a proven alternative to copper circuitry. This paper discusses the use of jet-dispensed Surface Mount Technology(SMT)adhesives for increased durability, lower component cost, and new form factor printed electronics. Jet-dispensing enables higher assembly speeds, accurate placement of multiple adhesives, smaller surface mount device (SMD) and Z-axis registration tolerance.

Today’s unique assembly challenges are comprised of complex PCB panelization, involving identical PCBs with a goal towards increased production capability, due to a reduced footprint of the Production Floor. Identical PCBs that are within the same panel, with uniform spacing in an array or carrier, need to be dispensed at the same time. All these high-mix challenges have gone mainstream and affects the real productivity and throughput. Existing manual dual head dispensing systems do not consider the rotational correction for the second head, which leads to yield loss. To eliminate the yield loss on second head, there is a mini XY drive system incorporated that provides fast and accurate dispensing to double the process capabilities over the same work area. Dynamic dual head dispensing uses a unique mini XY drive system on left head, mounted on a separate Z-axis, to dynamically control the position of the second head for accurately aligning to a second part, while synchronously dispensing both parts. Machine vision system performs the substrate alignment for each identical PCBs that are individually placed in a carrier, which provides greater potential for variation in offset and skew. During synchronous dispensing for the second part with the DDH, all the kinematic adjustment is performed with calculated values, from the skew angle and scaling factor. This technique guarantees increased productivity whilst maintaining yields through unsurpassed accuracy. DDH also provides the same level of adjustment and rotational correction for all step and repeated PCB’s, flex circuits and panel designs. If product contains odd number of units then either of the head can be programmed for dispensing while the others can’t.

This paper examines proven methods to determine the dot/line positional accuracy along with mass flow rate for both heads during synchronous dispensing. This paper will also address the challenges faced, and how the rotational correction can achieve up to 2X higher dispense productivity then existing single/dual head dispensing systems.

The drive for miniaturization of both commercial and aerospace/military technologies are not compatible with the current standard United States domestic PCB manufacturing processes at the volumes and lead times needed by OEMs and the Department of Defense. Even in technologies that are relatively widespread in domestic PCB manufacturing such as microvias, there are reliability concerns that prevents designers from exploring such options. The ability to repeatedly and reliably realize fine space and trace down to 25-microns would allow designers to reduce layer count, board footprint, sequential lamination cycles, and the use of stacked microvias at a reduced cycle time and cost. Currently, only offshore PCB manufacturers are close to achieving 25-micron space and trace using modified semi-additive processing (mSAP). The advances in offshore PCB manufacturing coupled with the obsoletion of larger component sizes threaten to disrupt the domestic supply chain as PCB manufacturers struggle to produce the necessary technology with the current process techniques. Extensively developed over the last twelve years, Averatek’s SAP process uses a thin layer of electroless to repeatedly and reliably realize down to 25-micron space and trace. Through a partnership with Calumet Electronics Corporation, a domestic high-volume PCB manufacturer that will act as the beta site for the 1st domestic SAP process, Averatek can now evaluate the integrity of their SAP process on an industrial production level scale. Averatek and Calumet Electronics Corporation will perform extensive qualifications of the use of Averatek SAP process for all subassembly levels of a multilayer board using a systematic approach that ensures traceability through the process from determination of targets, specification limits, quality goals, expectations to potential failures, and evidence of a robust process. The results of the qualification of Averatek SAP process will be used to further commercialize 25-micron space and trace across the domestic PCB industry, strengthening the technological capabilities of American manufacturers, OEMs and the defense supply chain.

The need for increasingly complex electronics combined with the obsolescence of larger component packages is driving innovation to provide alternatives to the traditional subtractive-etch fabrication process to reliably and repeatedly provide circuit layers with 25 micron or finer feature size.  Liquid Metal Ink (LMI™) technology is one of those innovations.

LMI™ allows a very dense thin catalytic seed layer which results in a very dense thin electroless copper layer that can then be used as a base for a much thicker electrolytic copper layer. Because the electroless copper can be so thin (0.1 μm) compared to the electrolytic copper (> 10um) very fine geometries can be defined with a simple flash etching process without risking undercutting the traces. This is the core technology that allows Averatek’s Semi-Additive Process(A-SAP™) to realize very fine feature sizes.

This process is compatible with most printed circuit board (PCB)processes and utilizes conventional PCB equipment. The resulting circuit features can resolve to 25 microns or below, providing a cost-effective solution to complex routing constraints that currently result in multiple lamination, stacked and staggered micro via solutions. LMI™ enables the mixing of a subtractive process with advanced processes such as A-SAP™ in several different ways. This mix and match approach can be used to build a Substrate Like PCB (SLP)and these combinations expand the practicality and performance of the circuit.  These very high-density circuit layers can stand alone or can be combined with layers created by the subtractive etch process that do not require such fine pitch. This combination efficiently results in the reduction of total number of layers and lamination cycles.

A higher manufacturing feasibility results from selecting the best manufacturing methodologies for each portion of the target system. This unique ability to combine standard and advanced processes will leverage the current domestic manufacturing infrastructure while extending capabilities well beyond the next generation interconnect.

The competitive pressures that electronics companies experience today are exceptional, even for an industry accustomed to a relentlessly high rate of innovation. Manufacturers are challenged to keep up with customization (lower volume and higher mix) and globalization. Material shortages and longer lead times means it is harder to maintain inventory. Compliance is also a challenge as more requirements are coming from customers, as well as new demands for example with electronic vehicles. New manufacturing best practices are crucial to meet these challenges.

Data collected from shop-floor drives the MES operation and the material flow. However, the value to this data does not stop there. Digitalization of the operation enables analysis and understanding of what is happening in the factory, why it is happening, and how to improve it. Although the amount of data generated by manufacturing operations is increasing exponentially, only a small portion of it actually gets collected, and an even smaller portion is analyzed in the electronics industry. In the use case presented here, we will demonstrate how manufacturers can benefit from collecting this data and applying analytics.

The biggest challenge with collecting data is turning big data into smart data that provides insight or foresight, can be understood as the point of consumption, and is immediately actionable on the shop-floor. There are three areas in which big data can be useful today in production to take immediate advantage from the amount of data.

The first is to improve our understanding of the process, so that we understand better the physical effects of what we are doing on the process. For example, we know that there might be an influence of the temperature at the reflow soldering in a certain extent, but we do not know if the temperature varies about three to four Kelvin in the reflow soldering process. We do not know whether this already has an impact on the AOI (automated optical inspection) quality or on the soldering quality. The analytics of big data could help us to understand that process better. If we understand our process better, we can buy better equipment and select the parameters more carefully. This could generate ROI in the long-term.

The second area is to improve quality. For example, we could better understand the impact of the incoming quality of our materials, which can reduce our scrap rate on a longer run. In this paper, we will present an example of how to use the data to improve quality in the printing process.

The third area is the most profitable: using the data to improve throughput. Once we have the data in-hand and are able to read the relevant information out of the data, we can judge from the overall quality on the line that the quality in all the single processes is so good, we can reduce the test level without jeopardizing overall quality.

The Vertical Segments of the Electronic Products Manufacturing Industry (Semiconductor, Outsourced System Assembly, and Test, and Printed Circuit Board Assembly) are converging and service offerings are consolidating due to advanced technology adoption and market dynamics. The convergence will cause shifts in the flow of materials across the supply chain as well as the introduction of equipment and processes across the segments. The ability to develop Smart Manufacturing and Industry 4.0 enabling technologies (e.g., big data analytics, artificial intelligence, cloud/edge computing, robotics, automation, IoT) that can be deployed within and between the Vertical Segments is critical. A Smart Manufacturing Technology Working Group (TWG) was formed by International Electronics Manufacturing Initiative (iNEMI) that included thought leaders from across the electronic products manufacturing industry. The TWG published a roadmap that included the situation analysis, critical gaps and key needs to realize Smart Manufacturing.

Robotic soldering is a growing market within the PCB Assembly industry and interest in robotic soldering equipment and applications is increasing every year. This method is more efficient than hand soldering and will aid in alleviating human mistakes. The robotic soldering process is more controlled and repeatable than a selective soldering fountain, and it can increase productivity and profitability. As the industry grows, we’ve found that there is not enough published data regarding this soldering technique. In this paper, we will present how cored wires with different flux percentages will affect robotic soldering performance. All wires used in this project were SAC305 alloy with a 0.020” diameter and3%, 3.5%, 4%,or4.5%of flux.