J-STD-001G Amendment 1 standard requires an OEM and EMS to qualify soldering and/or cleaning processes that result in acceptable levels of flux and other residues. Objective evidence shall be available for review. The use of the historical 1.56 μg/NaCl equivalence/cm2value for ROSE, with no other supporting objective evidence, is not considered acceptable for qualifying a manufacturing process.

The core concept for materials compatibility and residue acceptability is that of the qualified manufacturing process (QMP). In a QMP, manufacturing materials and processes used to qualify and validate production hardware confirm electrical performance in hot/humid conditions. The purpose of this research is to apply the methods documented in the standard to qualify and validate acceptable levels of flux and other residues when implementing a change in cleaning material and cleaning machine.

Findings and recommendations are reported from phase 1 of the Transient AMR(absolute maximum ratings) project, which is sponsored by the EOS/ESD Association and Industry Council on ESD Targets, and DfR Solutions. The project includes an industrywide survey about how AMRs of semiconductor products are determined and interpreted. Semiconductor manufacturers design the products to be reliable, as long as AMRs are never exceeded. Electronic system customers continue to increase their reliability expectations, especially in markets such as automotive. This project is of great importance to the electronics industry because customer returns of semiconductor parts continue to indicate that they have been overstressed, suffering electrically induced physical damage (EIPD). Transient excursions above AMR account for many failed parts, but root causes are difficult to discover as they happen unexpectedly, rendering the units unreliable. Manufacturers must ensure that published AMRs are clear and complete. Semiconductor customers and board and system designers must be educated to properly interpret AMRs on datasheets so they can take appropriate action to preserve the built-in reliability of semiconductor parts.

Project work is carried out at DfR Solutions, with some assistance by Industry Council representatives. Survey and literature search results will be summarized, including current practices regarding the determination, reporting, and interpretation of datasheet AMRs. Recommended best practices will be discussed. Case study examples from various companies will be shared anonymously.

High-frequency materials are characterized by several important parameters, including the dielectric constant or relative permittivity (εr) and the dissipation factor (Df). For those parameters to have meaning for circuit designers, they must be measured using methods that deliver accurate, repeatable results. However, circuit materials are characterized by many different test methods: For measuring εr, IPC has 12 different test methods.  Many other organizations, including ANSI and IEEE, have their own test standards for characterizing εr.Each measurement method provides detailed insights into the properties of the material it is testing, and the results of each test method may be correct, but they also may not agree. What follows is a review of different methods for measuring εralong with useful modifications and even some suggestions for new Dk measurement approaches.

This paper analyzes the reasons of inaccurate PCB impedance simulation of the traditional simulator and introduces a novel and cost-effective method for accurate PCB impedance simulation of any specific stack-ups. The new method doesn't need to extract material properties from prototype boards or empirical modified DK from PCB Fabs. The test results show the new method & tool have better precision simulation ability with deviation less than 2.5%, compared with traditional simulation tool. It can meet the requirement of less than 5% tolerance impedance to match the high speed & high frequency PCB design, and consequently leads to a more cost-saving and time-saving method to rapidly occupy the market.

The importance of signal integrity is emphasized as signal speed increases, and higher frequencies are applied. The PCB manufacturer uses SI coupons that can replace the in-product circuit to measure and calculate the signal loss. In this study, we tried to minimize the discontinuous path of Delta-L coupon by using the VIPPO (Via In Pad Plated Over) technique to improve the signal integrity. We compared the VIPPO-applied design that has minimal discontinuity with the conventional Delta-L design. In order to minimize discontinuity, circuits connected to pads and via holes were removed from the outer layer, and the pads were designed directly above the via holes. First of all, we simulated the optimized design that eliminated discontinuities using Signal Integrity Software, Simbeor. Second, we measured and verified Delta-L by using Introbotix's Accu-prober program. In the future, higher measurement frequencies will further increase signal loss due to unnecessary pathways and discrete signals, therefore minimizing the effects of discontinuity will be an important issue, and using the VIPPO technique will help to improve signal integrity.

Driven by rapid changes and markets, the electronics industry has seen massive growth over the past few decades. The short product life cycle has pushed PCB fabrication technology to its limits. Industry leaders continuously push innovations to be more competitive in the electronics manufacturing market space. In this era of electronics miniaturization, technologies that generate high yields with lower costs, such as High-Density Interconnects (HDI), Semi-Additive Processing (SAP), and Modified Semi-Additive Processing (mSAP), are widely utilized. Most of these technologies are not new to the electronics industry, but are common processes in IC substrate and PCB fabrication. They help maximize the PCB real estate usage by allowing fabricators and designers to build up multilayer devices. Figure 1 shows examples of multilayer designs that require multiple metallization and etching steps to achieve the desired designs and thicknesses.

Etching has become a crucial aspect of PCB fabrication. With the increasing number of layers, the risk of failure grows exponentially. Hence, a great deal of attention has been paid to the Cu deposit and how it reacts to etching. Higher technologies require many etching steps, during which uneven etching, pinhole formation, pitting or V-pitting, become significant issues [1]. These defects can cause severe reliability issues for the final product [2]. Innovative Cu electroplating solutions are required that produce Cu deposits with higher resistance to V-Pitting. Fabricators currently resolve these issues by baking the plated panels for several hours, which increases the process cost and negatively affects production output. The focus of this study was to investigate the underlying mechanism of V-pitting and to develop a process to withstand or resist the pitting. This phenomenon is called “V-piting“ due to the characteristic shape of the pits.

The process discussed here also showed excellent via fill and through hole (TH) plating capability in the same plating bath for core layers of HDI and IC substrates in a one-step DC process. Vias were filled with 49,000 psi, elongation > 25%). A bath aging study and a DOE were completed for the process. SEM, XRD, and FIB data will also be presented

KEYWORDS: Flash Etching, V-pit, Reliability, Via Fill, Trough hole, Pattern Plating, Metallization.

Phosphorus content in electroless nickel deposits, for PCB and electronic connectors, is a critical factor in controlling the nickel layer’s corrosion resistance and solderability. Improvements in X‐ray fluorescence (XRF) hardware and fundamental parameter software algorithms now allow for the direct measurement of the percent phosphorus (%P) under gold layers.

The development of nano-scale surface finishes over copper pads such as Electroless Palladium and Autocatalytic Gold (EPAG) has been evolving in the recent years due to ever increasing demands in terms of reliability, component miniaturization and signal transmission.

Scope of this paper is a full investigation of the production reliability of Electroless Palladium and Autocatalytic Gold. As soldering and bonding are both possible with EPAG and of special interest in the microelectronics industry, the solder joint reliability (SJR) and bonding results will be evaluated. Increasing I/O counts have led to ever decreasing cross sectional contact areas or, by default, an increase in solder performance expectations. The evaluation of this high solder joint reliability demand was satisfied by cold ball pull testing and high-speed shear testing (HSS).

To examine EPAG’s bonding abilities, the as-received (ASR) mode, as well as the aged condition at 150°C for 4h, were applied. Also, general storage reliability of the EPAG finish was simulated via ageing for 100 to 1000 h after bonding, assessing EPAG’s bonding performance over a broad process window. EPAG’s gold wire bond performance will be rated against ENEPIG finish. In addition to soldering and bonding, the reliability of a final finish is also reflected in its wetting behavior and adhesion; therefore, solder indicator, dewetting and solder spread testing were performed. Reliability against external, harsh conditions was tested via salt spray testing and compared to other common final finishes.

Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) is a well-accepted and established finish for high performance applications. The properties of the coating are determined mainly by the characteristics of the palladium layer and the type of the gold electrolyte used and have been investigated in various studies. 

In general, PdP or pure Pd coatings are available, which differ not only in their coating properties but also in their plating behavior and in the properties of the electrolytes used. The subsequent gold layer might be deposited by either an immersion type electrolyte or alternatively a reduction assisted gold bath which also will impact the final layer properties.

Looking back on a long experience of ENEPIG plating with pure Pd as well as with PdP, this paper will focus on the comparison of pure Pd and PdP deposits and the interaction with the gold electrolyte type in use.  The initial start reaction of the Pd bath is studied and the difference in the behavior of the PdP and pure Pd electrolyte was compared. Knowing that the crystallinity of the deposited layer is different for a pure Pd deposit compared to a PdP layer, the porosity was determined with the help of electrochemical as well as microscopical techniques to identify and judge the probability of a corrosive attack of the gold electrolyte to the underlying nickel. To be able to reliably judge the corrosive attack of the gold electrolyte, the corrosion was statistically evaluated by rating the number of corrosion events as well as the depth in the nickel deposit.

When comparing the performance of the finishes, considering the properties of electrolytes and the plating conditions, it becomes obvious that there is no single solution for all requirements. Rather, that the process allows manifold options to define the best conditions to the customer needs.

Key Words ENEPIG; Corrosion; Porosity; Solder Joint Reliability