The migration to large panel substrates in advanced packaging applications is principally motivated by cost considerations. However, it is occurring at a time when package processing is becoming more complex and demanding. New package architectures featuring heterogeneous integration (HI), such as Intel's EMIB, TSMC's INFO, and many others, present challenging new requirements in the fabrication process. With feature sizes less than 10 microns, increasing number of patterned layers, and vias between layers, these demanding process steps must be realized on wafer and panel substrates alike.

The traditional equipment set for large panel substrates typically uses bulk processing and is not designed for wafer-like process requirements. Thus, a new class of process tool is required to bridge this technology gap, maintaining the economy of scale of large panel tools while meeting the requirements of current and future package architectures. For electroplating process steps, a vertical tool architecture running a single panel per process cell makes it possible to directly apply advanced wafer plating technology to panel substrates.

Individual panels are loaded in a rigid holder to minimize warpage and provide the large currents necessary for plating large areas. An overhead transport conveys the loaded panels to a series of cells which carry out the necessary steps in the deposition process. The initial step is a vacuum prewet, which prevents the occurrence of air bubbles in deep features when the panel is introduced into a plating bath. A series of plating cells allows a stack of different metals to be deposited in a single pass through the tool. Each cell is customized for a particular metal and, with features such as multiple anode zones and pattern-specific shields, can be customized for each device. Efficient agitation is also adapted from wafer plating tools to provide the fastest and best quality deposition processes.

This paper will show that the improvements in feature density, deposition uniformity and void free via filling that are required for heterogeneous integration can be achieved in large panel processing, providing the desired cost reduction relative to wafer processing for interposers and other package structures.

The electroless deposition of Copper is widely used within the printed circuit board industry as it offers a simple and reliable method for metallizing holes, which subsequently enable multilayer PCBs. While the process as a whole continues to develop since its adoption, one point that has remained common is the need to activate those materials on which the Copper does not naturally deposit, namely the glass fiber bundles and epoxy matrix. Such activation processes are typically based on Palladium as this has been long proven to be a reliable method, however its use does not come without some penalties. The activation step is acknowledged to be one, and in some cases, the most expensive step within the electroless Copper process as a whole, and this is due to the cost of the Palladium metal itself. Historically this has always been a concern, but with the current cost of Palladium exceeding that of Gold, the desire for a “low cost” activator has increased dramatically in recent years.

Over the years, many suppliers have developed alternative processes utilizing conductive polymers or variations of carbon, and while these have been accepted within the market and have generally been found to operate at a lower cost, with decades of reliability data, and countless installations worldwide, the metallization of through holes with electroless Copper remains the preferred method for many applications. Hence the need for a “low cost” but high performance, Palladium based activator step remains as strong as ever.

This paper summarizes experiences gained while developing a new cost effective Palladium containing ionic activation system, we review the successes and issues found with early generations and then show that building on these experiences, a successful, low Palladium activation system can be provided that satisfies both the technical and commercial demands of today’s PCB market.

Surface Insulation Resistance (SIR) testing is a standard method used to characterize soldering and cleaning processes that result in acceptable levels of flux and other residues. Several different materials are used to assemble printed circuit cards. Residues can be present on the assembly from solder flux, solder paste, solder wire, underfill materials, adhesives, staking compounds, temporary masking materials, cleaning solvents, conformal coatings and more. Miniaturization of components increases risk due to tighter pitch, low standoff gaps, and residues trapped under the component termination.

In recent years, analysis of residues and their effects has shifted from a global examination of ionic residues (i.e. the entire assembly) to a more site-specific examination of spot or local contamination. The majority of an assembly surface may have acceptable levels of residues, with problem areas confined to a few components. Therefore, it was the desire to advance the state of the art in SIR testing and design cost-efficient test components and test vehicles that would allow an assembler to examine these problem point-sources of contamination. The goal of this research study was to design and evaluate an economical test board and laminate based components which mimic challenging components, and compare them to an accepted industry standard assembly, the IPC-B-52 standard test assembly.

A series of flux systems have been developed which would result in a reduced viscosity after reflow. This enables a high viscosity, high tack flux to be used to secure components at the component placement and reflow stage but ends up with a low viscosity flux residue after reflow, thus facilitating the flux residue to be cleaned. A technique for forming such special fluxes is to establish a temporary association force within the materials themselves, such as an acid-base association. This kind of association force can increase the apparent molecular weight and cause material viscosity to increase. After a heating process, one of the critical ingredients was evaporated, thus eliminating the association force, causing a decrease in the apparent molecular weight, and consequently a decrease in viscosity or an increase in mobility. The evaporation of one ingredient can be the result of one ingredient having a lower boiling point, or the decomposition of one ingredient during heating. A strong association force is desired to allow this acid-base combination approach to work. In this work, the volatile ingredient approach was less effective than a decomposable ingredient approach, presumably due to the formation of a bigger association cluster from the decomposable ingredient.

KEYWORDS Flux, viscosity decrease, reflow, clean, SIP, flip-chip

Certain high-reliability pockets of the electronics industry, such as telecommunications, defense, aerospace, and medical, often put great weight on the cleanliness of the finished PCBA. There are a few reasons why this cleanliness is deemed important, ranging from facilitating conformal coating adhesion, to cosmetics, to reliability. Years ago, PCBAs in these industry segments were often assembled with RMA classified solder pastes and fluxes and then cleaned to remove the flux residue. Many things have changed over the years, including the evolution of RMA solder pastes and fluxes into rosin-based no-clean solder pastes and fluxes, which are identified with a J-STD-004 classification of ROL0 or ROL1. The number of truly RMA classified soldering products has dropped dramatically, forcing many longtime RMA users to convert to modern rosin-based no-clean solder pastes and fluxes. For many of these converted applications, the legacy of cleaning for the sake of flux residue removal lives on for many of the same reasons that caused PCBA manufacturers to clean in the past. However, with the advent of no-clean solder pastes and fluxes and their forced continued Surface Insulation Resistance (SIR) improvement due to low standoff and bottom terminated components, have the enhanced properties of these modern formulations mitigated the need to remove rosin-based no-clean flux residues for the sake of electrical reliability? This paper will attempt to address this question by assessing the electrical reliability of no-clean solder paste flux residues using J-STD-004B SIR as the test method. In this work, IPC B-24 SIR coupons prepared with three commercially available rosin-based no-clean SAC305 type 4 solder pastes, two pastes classified as ROL0 or halogen-free and one classified as ROL1 or halogen-containing, reflowed with profiles with three different peak temperatures ranging from very cool to typical, will be compared to the electrical performance of clean bare IPC B-24 SIR coupons that have been exposed to the same reflow profiles as well as without any heat exposure.

While the intent of this paper is to show that cleaning is not always necessary for the sake of electrical reliability, without any doubt, there remain many scenarios where cleaning for the sake of removing the flux residues is appropriate such as applications involving conformal coating, underfilling, and high-temperature exposure (above the melting temperature of rosin), to name a few.

Every year, billions and billions of products are made and sold across the world. Each of these products, regardless of volume, are made in facilities that follow certain steps to assemble, test, and ship to customers. The steps that are taken to fulfill demand are an extremely interesting and valuable source of information. When modeled, simulated and analyzed, these steps can offer phenomenal insight on the overall process. This practice in the industry is called Discrete Event Simulation. Discrete Event Simulation, (namely DES) is the process of modeling a real-world phenomenon or system of operation as a sequence of discrete events. Discrete events in this context are described as instances that occur in a particular point in time with no change to the phenomenon or system between each event. Discrete Event Simulation is different than Continuous Event Simulation where the system is continuously changing due to a response to certain mathematical formulas and will not be covered in this paper. This paper will provide an overview of discrete event simulation in general, explain the different types of model taxonomy used in academia and industry, as well as discuss the importance and value of using these tools and practices in electronics manufacturing operations. Lastly, this paper will discuss challenges in adoption as well as a call to action for Discrete Event Simulation software providers and an outlook on where the industry is going from the perspective of Flex. In the context of this paper, “electronics manufacturing operations” refers to the assembly (both automated and manual), test (both automated and manual) and the shipping (both automated and manual) of electronic products.

Use cases, solutions and standards for single device traceability in the supply chain to enable root case analysis, recall containment, device pairing, yield and reliability improvement and liability protection.

Machine Learning 

Edge Computing

Edge AI

Demonstrated using a Case Study on HiP (Head in Pillow) defect detection