Printed circuit board manufacturers are continually challenged to fabricate denser solder mask patterns with smaller features to accommodate advanced electronic components. This trend is motivating manufacturers to adopt novel methods to achieve the required solder mask designs. One such method is direct imaging, which utilizes a controlled light source to directly expose the design image onto photosensitive solder mask material. Another method, termed herein direct jetting, uses inkjet printing to direct deposit jettable solder mask ink onto the circuit surface per the designed pattern. Both methods enable manufacturers to achieve fine solder mask features and circuit design registration with tight tolerances. The implementation of these methods in production requires testing and parameter setup as prerequisites, to ensure that the quality criteria are met, and the production process remains robust. This paper details the recommended steps to carry out such testing, included dedicated test vehicle designs that reduce the time and production resources required, while providing valuable data critical to defining process parameters and capabilities. The derived data is analyzed and compared with predefined performance criteria requirements to determine the optimal parameters that should be implemented in actual production.

In manufacturing multilayer printed circuit boards (PCBs), the PCB layer stack-up usually includes multiple plies of various types of prepreg along with the inner layer core material. Most of the layer stack-up process is manual operation relying on an operator to place the correct type and quantity of prepreg at designated dielectric openings. Missing or adding additional one or more plies of prepreg can result in a overall board thickness which will possibly still fall within its thickness specification limits but, its electrical property will be greatly affected (e.g. impedance, loss etc.). In this case, this abnormal board could possibly escape to customer unless detected by more expensive electrical property testing. Impedance measurement may catch the missing / extra prepreg for the dielectric layers related to impedance. Other layers without impedance control could still possibly escape. Considering impedance TDR measurement is time consuming and costly measurement process, a new lower cost approach was developed to detect extra / missing prepreg and validate the correctness of the stack-up. Our first approach is looking for statistical outliers for each given lot board thickness measurements after lamination. This approach is able to detect extra / missing prepreg, but its false alarm is too high due to missing one ply prepreg can be less than 0.002" thick which is generally less than one sigma of total board thickness. Thus, second approach using machine learning technique was developed with board thickness data (known bad and known good board thickness) and other features (e.g. prepreg type, lamination parameters etc.). From the model we developed and validated that our escape rate is still0% and its false alarm rate was reduced by 85%.

The advent of the Industry 4.0 Revolution and Internet of Manufacturing (IoM) has started to yield Smart factories, intelligent machines and networked processes, that have brought us improvements in yield and the ultimate in production efficiency and traceability. For most companies however, the cost and overhead of the implementation of Industry4.0 practices can seem like a large mountain to climb. Questions of cost, time, required resources and system-to-system communication protocol issues loom large, and can often hinder implementation.  The IPC CFX (Connected Factory Exchange) standard (IPC-2591)has been created to streamline this process, providing a standard communication protocol and messaging that is compatible across all SMT and other assembly equipment. In particular, this paper focusses on CFX as it applies to Reflow soldering, including adoption, integration, connectivity, messaging and the values that can be made available through CFX.

Electronics assembly can be delivered at competitive market prices only as long as the manufacturing process is continuously improved. Manufacturing companies are mastering with the help of Industry 4.0and simulation tools: a high degree of variance, continuously shrinking batch sizes, and fluctuations in order volume that are increasingly difficult to predict. The word “simulation” is defined as the computer-based modeling of the operation of a real-world process or system over time. With this definition in mind, it is easy to understand why simulation is ubiquitous in engineering and industrial organizations; imitating a real-world process or system allows experts to study the process or system they are interested in within a controlled environment. Manufacturing simulation allows companies to identify manufacturing bottlenecks and opportunities to increase throughput, identifying cost savings opportunities such as optimization of direct and indirect labor, managing inventory levels, and validating the expected performance of new or existing production facilities or value streams. Manufacturing simulation consists of plant simulation and process simulation. Plant simulation enables studies of material flows, bottleneck analysis at the area and line level, movement optimization, AGV movement simulations, and resource optimization studies. Process simulation enables studies of processes and operations to optimize sequencing of operations, robot and collaborative robots (“cobot”) operations, spatial risk analysis when humans are close to robots and cobots, and ergonomics simulation for optimal human movement. Simulation ensures compliance to Lean Manufacturing methodologies and removal of “waste.”  We answer the question; is manufacturing simulation applicable and effective in electronics assembly manufacturing?

This paper describes the design and implementation of several manufacturing simulation use-cases at an electronics assembly factory in Nanjing, China. This factory has six surface mount lines, fairly high product mix and variants, and also demands some high-volume production. Also, they have integrated circuit (ICT)and system tests, manual assembly lines, software loading stations, box-build cells, packing and labeling, shipping and, aftermarket service and depot repair. The chosen factory is an ideal candidate for testing the effectiveness of manufacturing simulation in electronics manufacturing. We describe the use-cases investigated, the approach, KPIs used to monitor progress, changes made to production, and the results of the theoretical simulation vs. actuals. We will also discuss using the Digital Twin of the factory and processes in additional use cases, such as sales evaluation and estimation validation. Finally, we publish results that may be used as an example of how other factories can use simulation to optimize throughput and cost in their factory to make steps forward in their digitalization journey and remain competitive.

With the ascent of Industry 4.0, the urgency of connecting to equipment on a manufacturing line is increasing. This article focuses on the electronics industry and summarizes what that interaction can entail, how it occurs, and the potential benefits. Interaction is broken into six areas: 1) automating transactions, 2) pulling data, 3 determining efficiency 4) sending settings/recipes, 5) dynamically changing settings and 6) applying machine learning. Seven communication techniques are also described: REST, SOAP, network socket, SECS/GEM, IPC Hermes and IPC CFX, and file transfer. Guidelines and current state-of-the-industry for each are given. Potential benefits for each are outlined along with suggested ways in which ROI can be calculated.

Within-application reliability and fail-safe processes paramount, aerospace applications present unique challenges for materials suppliers. As aerospace electronic devices increase in power density to accommodate higher function, and energy-efficient, high operating temperature wide bandgap (WBG) semiconductors become more prevalent, new materials with robust thermal management capabilities and higher operating temperature ranges are required.

Recently, a hybrid technology that marries the high thermal performance of pure silver sintering materials with the reliability of epoxy-based die attach pastes has been developed and is a promising solution to address these challenges. This hybrid technology offers similar electrical and thermal performance as sintering pastes but has exhibits less voiding and is process-friendly, much like that of traditional die attach pastes. This paper presents the results of an application study aimed at developing this unique technology in the field of high-power density devices for aerospace applications.

Conformal coatings are essential components for the microelectronics packaging industry. These functional coatings aim to protect electronic circuits from environmental factors such as heat and moisture. Typical coating formulations involve the use of epoxy, urethane and acrylic chemistries on polymer printed circuit boards (PCBs) leading to poor adhesion and failure to form void-free uniform coatings that follow the PCB skyline contour.

Plasma treatment is a novel method to increase the adhesion strength of the conformal protective coatings to PCBs through the removal of residual organic contaminants and surface activation. Poor adhesion can be a result of: i) incompatible materials, such as bonding polymers, ii) process residue: contaminants from fluxing, soldering and chemical treatments and iii) handling and storage conditions: fingerprints and dust. Plasma treatment under atmospheric pressure plasma (APP) conditions has emerged as an alternative solution for completely assembled PCBs which does not require a vacuum-based system. APP processes are fast and can be used for the treatment of selective areas of the board. The technology utilizes a dry gaseous medium and does not involve any harsh liquid solvent chemistries.  Air-based APPs contain gaseous species that can react and remove organic surface contaminants very rapidly.  Furthermore, they can be instrumental in the chemical functionalization and activation of the surface.  In this paper, case studies from the application of air-based APPs for the cleaning of PCBs and the improved adhesion of conformal coatings will be presented. 

The demand for smaller, faster and smarter electronic devices that can communicate to each other via wireless networks is stretching current communication systems to their limits. This rapid paced evolution is the driving force for the development of the next generation of network systems, the so-called 5G, to give the increased speed of communication and data capacity required.

One of the key factors, which will influence the development in 5G, is the range of frequencies at which data is transferred. Current 4G systems operate in relatively low frequencies of <6GHz. With the introduction of 5G systems, the requirement will be to run at much higher frequency band width; typical range will be from 6 up to >100GHz to enable faster mobile broadband, with low latency (the time taken for devices to respond to each other or a signal from another device) and the “internet of things” where compatible devices “talk to each other”.

With this transition to higher frequencies, the path of the electrical signal moves towards the edge of the copper traces into the so-called “skin” or the extreme outer edges of the copper trace. If this “skin” has been heavily roughened or etched, such as is the case in conventional multi-layer bonding enhancement processes, then there is an unacceptably high loss of the electrical signal.

To overcome this high signal loss material suppliers have been developing reliable high-speed dielectrics with low dissipation factors and dielectric constants. In combination with this, the contribution to signal loss from the bonding enhancement chemistry is under great scrutiny. Here, the challenge is to provide the most functionally reliable bonding process with the minimal surface roughening; but as the widely used Oxide Replacement bonding enhancement systems rely heavily upon surface roughening to give good bond strength this creates something of a challenge.

This paper highlights the challenges, developments and modifications made with conventional Sulphuric-Peroxide based Oxide Replacement bonding enhancement system to meet the low signal loss requirements for High Frequency applications, whilst maintaining the highest functional performance and bonding integrity needed for manufacture of reliable multi-layer PCB’s.