Tetrabromobisphenol-A (TBBPA) is the predominant flame retardant used in rigid FR-4 printed wiring boards (PWB). In
this application,the TBBPA is fully reacted into the epoxy resins that form the base material of the PWB. TBBPA’s
leadership position in the rigid printed wiring board market is due to several factors,which include reliable performance over
time. This paper will look at the benefits of TBBPA as a flame retardant in epoxy resin PWBs. It will also address the
current regulatory status of TBBPA. An update will be given on the regulatory and environmental status of TBBPA and
other industry assessments that compare TBBPA to alternative flame retardants for PB will be included.

We investigated the micro-void formation of solder joints after reliability tests such as preconditioning (precon) and thermal
cycle (TC) by varying the thickness of Palladium (Pd) in Electroless Nickel / Electroless Palladium / Immersion Gold
(ENEPIG) surface finish. We used lead-free solder of Sn-1.2Ag-0.5Cu-Ni (LF35). We found multiple micro-voids of less
than 10 ?m line up within or above the intermetallic compound (IMC) layer. The number of micro-voids increased with the
palladium (Pd) layer thickness. Our results revealed that the micro-void formation should be related to (Pd,Ni)Sn4 phase resulted from thick Pd layer. We propose that micro-voids may form due to either entrapping of volatile gas by (Pd,Ni)Sn4 or
creeping of (Pd,Ni)Sn4.

This paper will discuss a new approach to the final finishing for the PCB industry which is based on the use of an ultra-thin
fluoropolymer film as a protective coating to preserve solderability of the circuit board between manufacture and assembly.
The coating has been shown to extend the shelf life of the PCB by preventing oxidation and corrosion,and ensures excellent
solderability during assembly. The fluoropolymer coating is applied using a dry plasma deposition process,which eliminates
the use of harsh chemicals and waste streams associated with other surface finishes. The coating has been applied directly on
to copper,or can be used in conjunction with other surface finishes to act as a corrosion inhibitor when specific properties are
required,such as resistance to creep corrosion or tarnish.
Significant testing has been performed on the fluoropolymer coating to demonstrate its capability as a surface finish for the
PCB industry. The results of solderability testing,solder joint reliability testing and corrosion protection will be discussed.

As a surface finish,electroless nickel / electroless palladium / immersion gold (ENEPIG) has received increased attention
for both packaging/IC-substrate and PWB applications. With a lower gold thickness than conventional electroless nickel
/ immersion gold (ENIG) the ENEPIG finish offers the potential for higher reliability,better performance and reduced
cost.[1,2]
This paper shows the benefits by using a pure palladium Layer in the ENEPIG (Electroless Nickel,Electroless Palladium,
Immersion Gold) and ENEP (Electroless Nickel,Electroless Palladium) Surface Finishes in terms of physical properties
and in terms of gold wire bonding test results.

There are three key industry trends that are driving the need for temperature-dependent warpage measurement: the trend toward finer-pitch devices,the emergence of lead-free processing,and changes in device form factors. Warpage measurement has become a key measurement for analysis; prevention and prediction of interconnect defects and has been employed in failure analysis labs and production sites worldwide.
Over the past decade,the shadow moiré technique has become the method of choice for temperature-dependent warpage measurement. It is estimated that there are over 200 such machines installed worldwide. However,as the above-mentioned industry trends began to emerge,certain limitations of shadow moiré became apparent,such as camera resolution restrictions,schematic limitations on heating/cooling mechanisms,and data processing techniques that can affect accuracy. As a result of recent developments in projection moiré technology,these issues have been addressed,and the technique is poised to meet the future requirements of the microelectronics industry.
In this paper we discuss projection moiré as a new technique for warpage measurement of advance packages,with applications in failure analysis,new product qualification and process control. Projection moiré addresses many shadow moiré limitations,including camera resolution,heating uniformity and noise.
Key words: warpage,failure analysis,interconnect defects,moiré,shadow moiré,projection moiré,coplanarity.

With the advent of larger packages and higher densities/pitch the Industry has been concerned with the co -planarity of both
the substrate package and the PCB motherboard. The iNEMI PCB Co-Planarity Working group generated a snapshot in time
of the dynamic co-planarity of several PCB’s designs from four market sectors. This paper presents the summarized results
of the project’s investigation of the question if room temperature co -planarity measurements can predict the co-planarity at
Lead-Free assembly temperatures. This paper will also investigate the trends in dynamic co-planarity between market sectors
and global versus local area of concern measurements as well as share the learning and issues of undertaking dynamic co -
planarity measurements of PCB motherboards.

Coreless technology in package substrate has been developed to satisfy the increasing demand of lighter,smaller and superior electrical performance regarding as the future trend in electronic application. However,there are major challenges of reducing coreless substrate warpage in terms of both substrate manufacturing and assembly process. Substrate manufactures typically provide substrate warpage within satisfying customer’s specification which does not allow much margin left in assembly considering the number of reflows and curing profiles which the package undergoes during assembly. However,it is very difficult to provide satisfying this level of warpage because coreless substrate is one-third as thin as conventional one and does not use stiff core material. The key element for success in coreless technology is to solve the warpage issue at manufacturing site because the decrease of bare substrate warpage is important to improve the assembly yield. To figure out these problems,design optimization,mechanical/thermal treatment and low CTE material are suggested in this study. Final part discusses assembly result and issue for future work.

Due to the obsolescence of SnPb BGA components,electronics manufacturers that use SnPb solder paste either have to use
lead-free BGAs and adjust the reflow process or re-ball these components with SnPb balls. The reliability of Lead-Free and
Lead-Containing solder joints for BGA’s has been investigated after re-balling using optimal microscopy. The goal was to compare the quality of the connections for both options. For the lead-free BGA,voids produced by the release of volatile species in flux during soldering were present. Large voids have been observed at the interface component/solder. Using components that were re-balled did not show the amount of voiding observed for the lead-free BGA. Kirkendall voiding has been observed for the lead-free component at the component/solder interface. It has been therefore concluded that the use of the reballed components is to be preferred to adjusting the reflow profile and using lead-free components.

Accelerated temperature cycling was used to evaluate the thermal fatigue reliability for the case of backward compatible
assembly (mixed alloy,Pb-free BGA/SnPb paste) of a 3162 pin count,extremely large body (51.0 mm x 59.5 mm) ball grid
array (BGA). The BGA component was fabricated with Sn-4.0Ag-0.5Cu (SAC 405) Pb-free solder balls and surface mount
assembly was done using SnPb eutectic soldering profiles. The profiles were selected to simulate situations involving
incomplete mixing in order to study the effect of various levels of Pb mixing and microstructure on solder joint quality and
thermal fatigue reliability. Although the most common criteria for acceptable mixed alloy assembly are uniform or 100% Pb
mixing throughout the solder joint and complete ball collapse during reflow,these criteria can be difficult to meet with larger
BGA packages due to thermal issues. The effect of such imperfect mixing on reliability of large packages is unknown. The
test program included Pb-free,SAC405 assemblies to provide a reliability baseline comparison. Testing was done using a 0
to 100 ?C temperature cycle with 10 minute ramp and dwell times and post-cycling failure analysis was conducted on
representative test samples. Baseline characterization and failure analysis included optical metallography and scanning
electron microscopy (SEM). The thermal cycling test data and failure analysis results are discussed in terms of the
relationship to the initial as well as evolving Pb-free and mixed alloy microstructures. The reliability data indicate that mixed
assemblies can provide acceptable reliability,even in some cases when Pb mixing is not complete or uniform. However,
these results also show that warpage effects can increase the operating risk by reducing the process margin. Further,it is
shown also that the reliability likely is influenced more by the underlying Pb-free microstructure than by the Pb introduced
by mixed assembly.

Commercial-off-the-shelf ball/column grid array packaging (COTS BGA/CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronic packages. This talk briefly discusses an overview of packaging trends for area array packages from wire bond to flip-chip ball grid array (FCBGA) as well as column grid array (CGA). It then presents test data including manufacturing and assembly board-level reliability for FCBGA packages with 1704 I/Os and 1-mm pitch,fine pitch BGA (FPBGA) with 432 I/Os and 0.4-mm pitch,and PBGA with 676 I/Os and 1.0-mm pitch packages.