To keep up with shrinking system volume requirements for the Internet of Things and wearable devices while maintaining maximum device functionality requires an integrated approach to SoC and SiP optimization. To accomplish this we investigated the Direct Chip Attach (DCA) of a high density WLCSP onto the Printed Circuit Board (PCB) to obtain the smallest system footprint possible without compromising performance. Typically,to keep costs low,SoCs do not support the most aggressive interconnect density,and instead use wire-bond or large pitch flip chip packages to mount to the board. In this study,we take the opposite approach. Using DCA to attach the SoC directly to the PCB,we maximize the interconnect density between the board and silicon while keeping the cost low by eliminating the SoC package. This paper describes the impact of attaching a high performance SoC directly onto the board in terms of the PCB design,PCB fabrication and cost. We also investigate the SMT challenges of mounting the silicon directly onto the PCB at a 260 µm pitch array. Key metrics in this study include SMT yield,PCB routing,and PCB fabrication constraints as they relate to signal quality. In addition,the paper discusses future development challenges that face both the designers and PCB manufactures as they progress to support larger and denser direct chip attach products.

Modern consumer electronics are driving the adoption of smaller featured SMT devices such as 0.4 mm or smaller pitch CSP,and 01005’’ / 0402 metric discrete devices. Already roadmaps have been suggested to explore the use of smaller pitch CSP and 03015discrete devices,which are only around 64% the size of 01005 devices. On their own these challenges can be met by using stencils with thinner materials allowing sufficient area ratios to maintain the established safe area ratio guideline of 0.6% or higher. However when having to process fine feature devices along with larger devices such as connectors and RF shields,which usually require higher paste volumes to overcome co-planarity issues,the area ratio factors encountered in real production are dropping significantly below the conventional rule of thumb of area ratios having to be above 0.6 and in some instances below 0.5 area ratios. With this forced compromise in area ratio guidelines comes a compromise in process window robustness and subsequent print and even placement process quality. In order to try and redress this issue,different technologies have emerged in stencil materials and treatments combined with the use of finer grades of solder paste,but the question remains: “In isolation or by adopting a combination of these technologies is it enough,to establish a robust 03015 process?” This paper will review major steps considered and taken for the development of a robust 03015 process which was successfully Demonstrated at the company in-house show during Productronica in November 2013,and it will focus on the activities for the solder paste print process

This paper examines the use of Light Interferometry and the relevant parameters used to measure copper surface roughness before and after oxide alternative. Also discussed are the limitations and drawbacks of some of the traditional measurement parameters as they apply to copper surface roughness for conductor loss and signal integrity characterization and process control. In the PCB industry,we have seen minimal industry wide agreement on both the terminology,equipment and measurement parameter standards for the different foil types available from the copper foil and laminate suppliers. In the last 5 years,studies have indicated that high copper surface roughness is a significant factor in increased conductor losses. Specifically,the very high roughness of “Reverse Treat Foil” or “Standard Foil” whether used on the resist side or on the inner layer side was of greater significance than the micro roughness added by the oxide alternative bonding promotion treatment on the resist side.1Since then,the copper foil suppliers had focused on supplying copper foils with significantly reduced roughness on both sides of the foil in order to reduce high speed signal loss and preserve Signal Integrity. The traditional “Reverse Treat” or “Double Treat” foil typically has RSAR (Roughness Surface Area Ratio) of 1.0 to 1.2,Ra of 0.7 to 0.8 microns and Rz of 8-10 microns on one or both sides of the foil. “Standard” foil typically has similar roughness on the inner layer side and RSAR of 0.3 to 0.4,Ra of 0.3 to 0.4 microns and Rz of 3-4 microns with the smooth foil on the resist side. Now we are seeing VLP (Very Low Profile) with Rz 3-4 microns and HVLP (Hyper Very Low Profile) copper foils with 2-3 microns Rz on both sides. Concurrently,we have been exploring the measurement of the “resist side” copper surface micro roughness following oxide alternative process,or bonding promotion treatment,to better understand its role in Signal Integrity and establish in-process control measurement capability.

In technology tendency,signal integrity performance gets more critical upon today’s higher signal transmission speed and quantity demand in every field of applications such as computer CPU and GPU chipset levels,system operation frequency and a variety of communication bus and cable like PCIexpress,SATA II and AGP bus for computer system. Signal communication speed will shift from 5~10Gbps range up to ~25Gbps depending on applications. Here we propose a simplified,easy and stable PCB wide bandwidth electrical properties extraction methodology over 20GHz to evaluate and to measure print circuit board’s electrical performance and its variation over environmentalparameters,process parameters,like temperature,moisture,thermal cycling and stress. The method is based on the theory of microwave measurement calibration and in-plane stripline mathematical model and integrated with instrument control interface technology. It’s using a simple two single-end or two differential pair in different length circuit traces without regular full SOLT,TRL calibration circuits or others disc structures. Measuring these two lines scattering parameters under desired conditions like temperature at this case study,the purely traces insertion loss,characteristic impedance and Dk/Df of constructed material over frequency are extracted.

The electronics industry is driven by constant technological changes,which have brought improved innovative products to the marketplace. These advances have placed high demands on material performance,such as low dielectric constants (Dk),low loss tangent (Df),low moisture uptake and good thermal stability. Epoxy resins are an essential material of the electronic industry. [3] Significant enhancements of epoxy resins have been obtained through the use of PPE macromonomers. However,there is a limit on the performance that can be delivered from epoxy-based resins. Therefore,non-epoxy based dielectric materials are used to fulfill the need for higher capability. The focus of this paper is on the use of PPE macromonomers to enhance the performance of cyanate esters laminates.

The paper will propose to present a technology for the fabrication of Printed Circuit Boards (PCBs),used primarily in high-power RF/millimeter wave applications,which involves the use of a thermally engineering metalized layer with superior thermal characteristics and a ceramic-matched co-efficient of thermal expansion (CTE). The resulting PCBs allow the user to direct die-attach high-power RF die,such as GaA and GaN devices through a cavity in the outer core layer(s),directly to the thermal layer below; and then wire bond to the surface conductive layer. The thermal characteristics of the engineered material quickly and efficiently evacuate the significant heat generated by the die while CTE “anchors” the resulting PCB substrate assuring the reliability of the die-attach wire bonds.

Thermal management is a critical element in the design and manufacturing of printed circuit boards (PCBs) for a wide range of applications. Quite simply,heat can be destructive. The more effectively that heat is dissipated from a PCB,the better the opportunity for a long,reliable operating lifetime for that PCB. Attaching a heat sink to the PCB can be an important step in the thermal management process,and several methods are available for attachment,including sweat soldering,fusion bonding,mechanical press fit,and the use of thermally conductive adhesive. Each approach has strengths and weaknesses,although the use of thermally conductive adhesive may be the simplest procedure. A number of studies performed with Thermally and Electrically Conductive Adhesive (TECA) materials may help to shed some light on the benefits of using such thermally conductive adhesives,and these studies will be reviewed in three segments: fabrication techniques and testing,thermal performance,and electrical performance.

Pad cratering failure has emerged due to the transition from traditional SnPb to SnAgCu alloys in soldering of printed circuit assemblies. Pb-free-compatible laminate materials in the printed circuit board tend to fracture under ball grid array pads when subjected to high strain mechanical loads. In this study,two Pb-free-compatible laminates were tested,plus one dicy-cure non-Pb-free-compatible as control. One set of these samples were as-received and another was subjected to five reflows. It is assumed that mechanical properties of different materials have an influence on the susceptibility of laminates to fracture. However,the pad cratering phenomenon occurs at the layer of resin between the exterior copper and the first glass in the weave. Bulk mechanical properties have not been a good indicator of pad crater susceptibility. In this study,mechanical characterization of hardness and Young’s modulus was carried out in the critical area where pad cratering occurs using nano-indentation at the surface and in a cross-section. The measurements show higher modulus and hardness in the Pb-free-compatible laminates than in the dicy-cured laminate. Few changes are seen after reflow – which is known to have an effect -- indicating that these properties do not provide a complete prediction. Measurements of the copper pad showed significant material property changes after reflow.

Many opportunities exist for flexible circuits in high temperature applications (Automotive,Military,Aerospace,Oil and Gas). Flex circuits in these applications have been hindered by a lack of materials that can survive higher temperatures. Some materials,especially some thermoset adhesives,break down over time at higher temperature,becoming brittle or losing adhesion to copper. Polyimides tend to perform much better under high temperature. The other issue is the lack of good test methods to verify that flex materials can survive higher temperatures. Several methods for testing copper clad laminates exist but there are very few for coverlays and bondplies. We will discuss different test methods for measuring high temperature capability including the new IPC Service Temperature test. We will also report on test results for various flexible materials and our recommendations for the best flexible materials for high temperature applications. This will include development work on new flex materials for high temperature applications.

The use of microvias in Printed Circuit Boards (PCBs) for military hardware is increasing as technology drives us toward smaller pitches and denser circuitry. Along with the changes in technology,the industry has changed and captive manufacturing lines are few and far between. As PCBs get more complicated,the testing we perform to verify the material was manufactured to our requirements before they are used in an assembly needs to be reviewed to ensure that itis sufficient for the technology and meets industry needs to better screen for long-term reliability. The Interconnect Stress Testing (IST) protocol currently used to identify manufacturing issues in plated through holes,blind,or buried vias are not necessarily sufficient to identify problems with microvias. There is a need to review the current IST protocol to determine if it is adequate for finding bad microvias or if there is a more reliable test that will screen out manufacturing inconsistencies. The objective of this research is to analyze a large population of PCB IST coupons to determine if there is a more effective IST test to find less reliable microvias in electrically passing PCB product and to screen for manufacturing deficiencies. The proposed IST test procedure will be supported with visual inspection of corresponding microvia cross sections and Printed Wiring Assembly (PWA) acceptance test results. The proposed screening will be shown to only slightly affect PCB yield while showing a large benefit to screening before PCBs are used in an assembly. The test vehicles will be production-built hardware from multiple suppliers over a 4-year time period,of 2010 to 2014,of polyimide and epoxy constructions. Both 152-µmand 203-µmdiameter microvias will be reviewed. It will be shown that theinitialIPC-TM-650 Number 2.6.26 DC Current Induced Thermal Cycling Test,dated May 2001 default conditions were not sufficient to adequately screen for microvia manufacturing inconsistencies and that,with a few changes to the current testing,high-reliability product could be screened quickly for current technology.