How to Manage Wave Solder Alloy Contaminations

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European electronics industry is soldering with lead-free alloys for one decade now. In this period not only the knowledge of the alloys in the assembly process has been improved,but also a high amount of data is collected. Technology has changed over these ten years including the prices of the metal. The dramatic increase of operation costs due to high metal prices forces engineers to look more critical to their wave soldering process. Balver Zinn has been studying the consistency of alloys in wave soldering process since the implementation of lead-free. The lab measures the contamination of lead-free solder alloy samples of their costumers and thus enables them to do statistical process control on the alloy composition. In these ten years of lead-free soldering over 25.000 samples were investigated looking at contaminations of lead,the drift of the Copper content,and or increase of iron in the alloy due to solder pot erosion. Analyzing this data returns a lot of information on copper leaching for the different alloys. How to manage the copper level in the lead-free solder alloy to avoid an increase of soldering defects will be discussed. The data of these alloy analysis contains samples of all kind of production environments: low and high volumes,different solder machines and solder pot contents,solder temperatures,alloys,board finishes and inert systems versus soldering in air. With this presentation we try to give guidelines for the costumers how to control their alloy in order to minimize solder defects in combination with keeping the metal consumption/operational cost as low as possible.

Author(s)
Gerjan Diepstraten
Resource Type
Technical Paper
Event
IPC Midwest 2011

A Review of Issues and Next Steps in Moving From Sn3Ag0.5Cu to Low Silver Solder Alloys

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The implementation of the European Restriction of Hazardous Substances (RoHS) Directive has initiated an electronics industry materials evolution. Printed wiring board laminate suppliers,component fabricators,and printed wiring assembly operations are engaged in numerous investigations to determine what lead-free (Pbfree) material choices best fit their needs. The complexities of Pbfree soldering process implementation insures a transition period in which Pbfree and tin/lead solder finishes will be present on printed wiring assemblies for many electronic product segments. One of the component surface finishes being offered by electronics industry component fabricators is 98% tin - 2% bismuth
(98Sn2Bi) as a Pbfree component finish option. This presentation documents an investigation of a solder joint integrity assessment of tin/bismuth component surface finishes in both tin/lead and Pbfree soldering processes under thermal cycle conditions. The investigation results are also compared/contrasted with other industry published data sets.

Author(s)
Jasbir Bath
Resource Type
Slide Show
Event
IPC Midwest 2011

Thermal Cycle Solder Joint Integrity Assessment of SnBi Plated Components

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The implementation of the European Restriction of Hazardous Substances (RoHS) Directive has initiated an electronics industry materials evolution. Printed wiring board laminate suppliers,component fabricators,and printed wiring assembly operations are engaged in numerous investigations to determine what lead-free (Pbfree) material choices best fit their needs. The complexities of Pbfree soldering process implementation insures a transition period in which Pbfree and tin/lead solder finishes will be present on printed wiring assemblies for many electronic product segments. One of the component surface finishes being offered by electronics industry component fabricators is 98% tin - 2% bismuth (98Sn2Bi) as a Pbfree component finish option. This presentation documents an investigation of a solder joint integrity assessment of tin/bismuth component surface finishes in both tin/lead and Pbfree soldering processes under thermal cycle conditions. The investigation results are also compared/contrasted with other industry published data sets.

Author(s)
David Hillman
Resource Type
Slide Show
Event
IPC Midwest 2011

Low Silver Solder Alloys with Good Drop Shock and Thermal Cycle Reliability

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SAC105 was shown to have better drop shock reliability than SAC305 however SAC105 thermal cycle performance was not necessarily as good at SAC305. Small quantities (0.1% or so) of some elements appear to improve both drop shock and thermal cycle reliability of SAC105. This paper will be an overview of work performed to demonstrate this phenomenon.

Author(s)
Ronald Lasky
Resource Type
Slide Show
Event
IPC Midwest 2011

Key Issues in Bottom Termination Component (BTC) Design and Assembly for Improved Reliability and Yield

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With the release of IPC 7093,"Design and Assembly Process Implementation for Bottom Termination SMT Components," earlier this year,the term BTC is the newest acronym to enter the world of SMT. BTCs are very much like the BGAs but without the balls. Excellent electrical and thermal performance combined with lowest package cost has made this package very popular especially in mobile products. However,the absence of balls changes practically all aspects of design and manufacturing SMT assemblies using BTCs. The connection between the package and PCB is essentially like a postage stamp which poses challenges in both design and assembly of BTCs to achieve acceptable reliability. And achieving good yield is also a challenge since both the package and PCB must be perfectly flat. Any warpage in package and PCB has to be compensated by solder paste but too much paste creates voids and package floating and too little paste causes opens and insufficient solder resulting in premature failure. Based on the design and assembly guidelines in IPC 7093 co-chaired by the author,this presentation will focus on key issues in design and assembly to reduce defects and improve reliability.

Author(s)
Ray Prasad
Resource Type
Slide Show
Event
IPC Midwest 2011

Thermal Pad Design at QFN Assembly for Voiding Control

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Quad Flat No Leads (QFN) package designs receive more and more attention in electronic industry recently. This package offers a number of benefits including (1) small size,such as a near die size footprint,thin profile,and light weight; (2) easy PCB trace routing due to the use of perimeter I/O pads; (3) reduced lead inductance; and (4) good thermal and electrical performance due to the adoption of exposed copper die-pad technology. These features make the QFN an ideal choice for many new applications where size,weight,electrical,and thermal properties are important. However,adoption of QFN often runs into voiding issue at SMT assembly. Upon reflow,outgassing of solder paste flux at the large thermal pad has difficulty escaping and inevitably results in voiding. It is well known that the presence of voids will affect the mechanical properties of joints and deteriorate the strength,ductility,creep,and fatigue life In addition,voids could also produce spot overheating,lessening the reliability of the joints. This is particularly a concern for QFN where the primary function of thermal pads is for heat dissipation. Thermal pad voiding control at QFN assembly is a major challenge due to the large coverage area,large number of thermal via,and low standoff. Both design and process were studied for minimizing and controlling the voiding. Eliminating the thermal via by plugging is most effective in reducing the voiding. For unplugged via situations,a full thermal pad is desired for a low number of via. For a large number of via,a divided thermal pad is preferred due to better venting capability. Placement of a thermal via at the perimeter prevents voiding caused by the via. A wider venting channel has a negligible effect on voiding and reduces joint continuity. For a divided thermal pad,the SMD system is more favorable than the NSMD system,with the latter suffering more voiding due to a thinner solder joint and possibly board outgassing. Performance of a divided thermal pad is dictated by venting accessability,not by the shape. Voiding reduction increases with increasing venting accessability,although the introduction of a channel area compromises the continuity of the solder joint. Reduced solder paste volume causes more voiding. Short profiles and long hot profiles are most promising in reducing the voiding. Voiding behavior of a QFN is similar to typical SMT voiding and increases with pad oxidation and further reflow.

Author(s)
Yan Liu
Resource Type
Slide Show
Event
IPC Midwest 2011

Design and Process Implementation Principles for Embedded Components

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Vern Solberg is an independent consultant specializing in SMT and microelectronics design and manufacturing technology. He has served the industry for more than twenty-five years in areas related to both commercial and aerospace electronic products and is active as an author and educator. Solberg holds several patents for 3D semiconductor packaging innovations and is the author of Design Guidelines for Surface Mount and Fine-Pitch Technology a McGraw-Hill publication and furnishes the ‘Designers Notebook’ column for SMT magazine. Vern was also awarded the prestigious ‘Raymond E. Pritchard Hall of Fame Award’ and is currently an active member of IEEE,SMTA,IMAPS and the IPC,the industries standards development organization for electronics. Current IPC activity- Co-Chairman of the task group currently developing the IPC-7092,‘Design and Assembly Process Implementation for
Embedded Components’.

Author(s)
Vern Solberg
Resource Type
Slide Show
Event
IPC Midwest 2011

Evolution Toward a Workmanship Standard For Underfill

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There is no issued industry standard for the workmanship of underfills – either from the perspective of visual examination (a la A-610) or by more intrusive techniques like cross-sectioning. This presentation will highlight what has been put together and submitted to the appropriate IPC standards committee for consideration. Further some challenges faced by trying to meet this standard may be delineated as
well.

Author(s)
Bev Christian
Resource Type
Slide Show
Event
IPC Midwest 2011

Analytical Procedures for Portable Lead-Free Alloy Test Data: State of Merge of iNEMI and SPVC Documents

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The IPC Solder Products Value Council,in cooperation with iNEMI and a group of industry experts,has developed a protocol for testing the physical properties of lead free solder alloys. This presentation will review the status of the protocol’s development,the status of a round robin of the protocol’s test repeatability and then briefly discuss the prospect for developing better reliability models using creep data testing as described in the protocol.

Author(s)
Greg Munie
Resource Type
Slide Show
Event
IPC Midwest 2011

Common Mistakes in Electronic Design

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Board-level designers are constantly expected to cram more computational power,into a smaller space,at lower cost,and accomplish this task in less time and with fewer resources. In this rush to meet customer requirements,common and costly hardware design mistakes are often made. Examples include part selection,component placement,board layout and specifications,and understanding the role design plays in ensuring long-term reliability. This presentation provides hardware designers with case studies of some common mistakes and the process by which these mistakes were inserted or overlooked during the design process. The presentation will also provide a checklist to avoid these mistakes,why these mistakes caused failures,and optimized corrective actions necessary to avoid these problems,but still ensure a successful product launch.

Author(s)
Craig Hillman
Resource Type
Slide Show
Event
IPC Midwest 2011