Electronic assembly innovations drive more performance using highly dense interconnects. Assembly residues may increase the risk of premature failure or improper functionality. The challenge for OEMs is to quantify safe residue levels and how residues impact long term reliability and functionality of hardware. To compound this problem,the question of “how clean is clean enough” is more challenging as conductors and circuit traces are increasingly narrower.
Highly dense bottom termination components decrease conductor pitch,spacing and standoff heights. The problem is that current spacing trends can yield spacing between printed circuit traces as small as 2 mils. As electrical fields rise,contamination at these narrower traces becomes more problematic due to voltage swings,high frequencies,leakage currents,and high impedance.
The purpose of this research is to build a new test board that provides a more accurate correlation and prediction of assembly residues to one or more aspects of long term reliability. The test board will be populated with a series of bottom termination components and cleaned. The research will follow a three phase strategy:
• Phase 1: PCB layout/Component Library Selection Geometries/Sample Size
• Phase 2 DOE Matrix: PCB Surface Finish,Flux & Cleaning Chemistries,Cleaning Systems/Analysis Techniques using IC,IR,HPLC,GCMS
• Phase 3 Conclusion: DFM approach for PCB designers layout relative to cleanliness limitations to establish a defined PCB design layout to facilitate an acceptable electrical measurement (i.e. fork,divider,capacitance,etc.) via a library of components (i.e.,QFN,PLCC,BGA,etc.) geometries to test cleaner/chemistries capabilities

Printed circuit board (PCB) material properties and surface roughness directly influence attenuation and NEXT/FEXT crosstalk signal integrity of high speed digital interconnect design. Balancing performance,cost,and ease of fabrication requires a quantitative understanding of the impact that the dielectric material and surface roughness will have on the performance of the signal path through gigabit PCBs,backplanes,cable assemblies and connectors. An in-depth understanding of how the material will perform when used to fabricate 25+ layer count boards with thicknesses over 250 mils is required. This paper provides a survey of these problems and of possible measurement solutions,including characterizing signal path integrity,power/ground integrity,materials properties,package/fixture measurement challenges and the surface roughness of copper signal traces.

In this evaluation we will show an ionic residue comparison using Umpire 2 boards that were top and bottom surface mounted with standard reflow and selective wave soldered on the connector and B-24 comb patterns. For this evaluation,30 boards were processed using a no clean flux with lead-based soldering parameters. Three groups were evaluated,Group A (not cleaned),Group B (water only cleaned) and Group C (saponified steam cleaned). The 30 assemblies and 3 unprocessed boards were SIR tested for electrical performance and then each assembly was C3 tested in three locations (0.1 in2 area) and then the entire board was bag extracted.

Counterfeit and substandard parts and components have been a recurring theme in practically every market. For the last several years,the largest concern has been in the military and aerospace industries. Many of these re-marked and recycled parts are coming back into the US from electronic waste that was sent overseas. In an attempt to mitigate risk and potentially eliminate use of counterfeit and substandard parts,it is important to develop a counterfeit inspection procedure for incoming materials. This inspection can be as basic as a visual examination but becomes more successful at identifying potential counterfeit components and parts when a few more techniques that are advanced are employed. This webinar will present background regarding the counterfeit market as well as provide information on various tests and testing techniques for identification of counterfeit parts.

The breadth of materials and processes used in today’s electronic assemblies may make it impossible to predict SIR/ECM performance without adequate testing of material and process combinations. Some materials behave very well when tested singularly,yet behave very poorly when used together. This is of great importance as most possibilities coexist on real-world industry product. This presentation will provide a survey of actual results with broad,non-brand specific categories of materials and process combinations. Some trends will be presented to help the audience appreciate areas of possible concern.

High yields in the stencil printing process are essential to a profitable SMT assembly operation. But as circuit complexity continues to increase,so do the challenges of maintaining a successful solder paste deposition process. To help assemblers address the challenges presented by evolving technologies,stencil suppliers have provided a variety of options in stencil technology,including new foil materials,manufacturing processes and coatings.
A study was undertaken to quantify the effects of stencil material on paste deposition in high volume production processes. The experiment focused only on laser cut stencils,and compared the typical stainless steel,non-electro polished foils with electro polished stainless steel,fine grain stainless steel,and electroformed nickel. The DOE strived to maintain consistency of all other variables involved in the process,changing only the stencil material. The test vehicle design varied theoretical area ratios from 0.50 to 0.75 in 0.05 increments (actual area ratios varied between 0.48 and 0.77). Output variables were paste deposit volumes,which were expressed as transfer efficiencies based on measured (actual) aperture volumes.
The transfer efficiencies of the four materials are compared and performance differences are discussed. High magnification photographs of the aperture walls provide visual images of the wall topographies. The effect of electro polishing is shown and discussed.

In electronics design,Computer Aided Design (CAD) tools manage part data in a logical schematic view (a part symbol) and a physical PCB view (a part footprint). Yet,a part has a third view,which CAD tools ignore – its supply data (Manufacturer part number,variant,distributor,etc). To manage this manufacturing view a broad class of tools known as Product Lifecycle Management (PLM) have evolved.
A substantial chasm exists between the manufacturing and engineering views. More specifically,part data known to the supply chain (managed through PLM tools) and performance and specification data known to the engineering world (managed through CAD tools) must be manually integrated and managed by the design team. This leads to a substantial amount of redundant data entry into both tool chains with any error resulting in an inconsistency between design intent and fabrication.
In this work we introduce an entirely new approach to bridging the tool-chain divide – a web-based architecture we call FriedParts. FriedParts exploits the recently available database-driven parametric part interfaces of CAD tools (like Cadence’s Component Information System or Altium’s Database Library Components) and web 2.0 automation to crawl data information providers like Octopart,Inc. and Digikey,Inc. and tie this information directly into the CAD tool at design time. It uses heuristics to suggest CAD symbols and footprints. Part search is handled from the website where cloud computing accelerates the search performance. The materials bill output from the CAD tool is then fed back into FriedParts which can automatically find second-source distribution,find alternate manufacturers,optimize purchasing,and perform other PLM functions. The amount of data entry by the designer is brought to almost zero. FriedParts stores the actual CAD data (part libraries) fostering verification and collaboration.
In a user case study,the average time to enter Digikey part number P1.0KGCT-ND,a Panasonic 1K-Ohm surface-mount resistor,was 6.1 seconds – including all of the round-trip time to the server. Compare this with more than ten minutes to do the identical task using a combination of an Excel-based CIS database and a popular online-based commercial PLM product. Further,the FriedParts solution resulted in zero data-entry errors and perfect user compliance,whereas three errors (inconsistencies) were found between the data entered into Excel and the online PLM.
Conceptually,FriedParts is a technology demonstration of the idea that CAD and PLM should share a single parts database to eliminate synchronization effort and errors,should exploit online information sources,and should simplify and automate data-entry tasks. FriedParts is open-source and will also be made available as a free service.

Most of electronic components on a printed circuit board assembly (PCBA) are surface mount components assembled using solder paste material. Having a good solder paste material is very critical for having a high yield and reliable product. There is a strong correlation between the SMT defects to solder paste quality1,but there is limited published information on the evaluation procedure and requirements for a good solder paste material.
This paper discusses the strategy and methodology for selecting a good lead-free solder paste material for volume manufacturing uses. A statistical and methodological evaluation approach will be addressed in details. It shows how to screen the solder paste candidates for quality using printability tests,slump test,solder ball test and wetting tests and how to select a robust solder paste material using a design of experiment. The performance of lead-free no clean solder paste,lead-free water soluble solder paste,halogen containing solder paste and halogen free solder paste will be compared. Characteristics and requirements of a good lead free solder paste material are also outlined.

The challenges of successful solder printing in the High Volume / Low Mix cell phone environment,which is linked with the continuing trend to miniaturize electronic assemblies,requires a new approach to improve the printing capabilities and process repeatability. Actual stencil technologies such as electroform or laser-cut limit the stencil opening due to aspect and area ratios at the smallest devices producing a very tight process window. It’s here that Nano Technology will assist in the printing process. Using Nano Coating over the stencil openings to smooth the surface and improving the paste release,helps reducing aperture openings,and creates a wider process window. Additionally,panel stretch and PCB fabrication tolerances produce a silent non constant variable that moves the process outside the quality printing window,without obvious signs of variation.
To obtain an advantage,and successfully implement this technology,the process requires new controls of chemical and parameter settings. We will discuss some aspects of process optimization and how this very tight process window is affected,by identifying the challenging process parameters,including circuit board fabrication,component pad design,and printing parameters (speed,separation,pressure,etc.). This printing study will consider the effects of print speed,print pressure,and separation speed,to optimize solder paste transfer efficiency (TE) to establish an statistical process control that gives real time warnings of an out of control printing process. We will discuss our data results which will include the advantage of using Nano stencil vs. E-Fab and Laser NiEX. TE improvement is 5% at the smallest stencil aperture across a panel of 4 images. The cleaning speed significantly reduces defects from 2% with a 50mm/sec,to zero defects using 20mm/sec. By improving the TE by 5% will increase the number of prints without a paste bridge on any board,even up to10 prints between cleaning.

We describe a coupon design that makes available,in an elegant and efficient way,information unattainable even from multiple-coupon vertical cross-sections. The new design allows quantitative determination of annular ring and of breakout angle on internal layers of printed circuit boards. The new design provides evidence for compliance (or lack of it) with user requirements regarding internal annular ring and breakout angle. It permits assessment of the adequacy of design rules and allows collection of data for statistical process control or process optimization via designed experiments.