Wetting balance testing has been an industry standard for evaluating the solderability of final finishes on printed circuit boards (PCB) for many years. A Wetting Balance Curve showing Force as a function of Time,along with the individual data outputs “Time to Zero” T(0),“Time to Two-Thirds Maximum Force” T(2/3),and “Maximum Force” F(max) are usually used to evaluate the solderability performance of various final finishes. While a visual interpretation of the full curve is a quick way to compare various test results,this method is subjective and does not lend itself readily to a rigorous statistical evaluation. Therefore,very often,when a statistical evaluation is desired for comparing the solderability between different final finishes or different test conditions,one of the individual parameters is chosen for convenience. However,focusing on a single output usually does not provide a complete picture of the solderability of the final finish being evaluated. In this paper,various models here-in labeled as “point” and “area” models are generated using the three most commonly evaluated individual outputs T(0),T(2/3),and F(max). These models have been studied to quantify how well each describes the full wetting balance curve. The solderability score (S-Score) with ranking from 0 to 10 were given to quantify the wetting balance curve as the result of the model study,which corresponds well with experimental results.

The risk associated with whisker growth from pure tin solderable terminations is fully mitigated when all of the pure tin is dissolved into tin-lead solder during SMT reflow. In order to take full advantage of this phenomenon,it is necessary to understand the conditions under which such coverage can be assured. A round robin study has been performed by IPC Task group 8-81f,during which identical sets of test vehicles were assembled at multiple locations,in accordance with IPC J-STD-001,Class 3. All of the test vehicles were analyzed to determine the extent of complete tin dissolution on a variety of component types. Results of this study are presented together with relevant conclusions and recommendations to guide high reliability end-users on the applicability and limitations of this mitigation strategy.

Ever since there has been a widespread usage of surface mount parts,the trend of continued shrinkage of devices with ever finer pitches has continued to challenge PCB assemblers for the rework of same. Todays’ pitches are commonly 0.5 to 0.4mm with packages of tiny outline sizes 5 -10mm square,making the rework of such devices a challenge. In addition to the handling and inspection challenges associated with such devices comes the board density. Spacing to neighboring components continues to be compressed so the rework techniques are constantly challenged so as not to damage neighboring components. The objective of any rework process is to duplicate as closely as possible the original manufacturing process but not disturbing neighboring components while at the same time meeting the original specifications and assembly criteria of the PCB. For the rework of a given area or bottom-terminated device this is typically accomplished by using a miniature version of the original printing SMT stencil albeit for the site location only. That being the process that will be characterized in this study,there are two basic types of stencils which can be used to print solder paste onto the PCB. In one case the miniature rework stencil is a shrunken version of the SMT stencil being made from some version of stainless steel of the same thickness of the original stencil. In the other configuration the rework stencil is a single use type made from a flexible plastic film and is adhesive-backed.

Certain types of nano-coated stencils dramatically improve the transfer efficiency of solder paste during paste printing. These nano-coatings also refine the solder paste brick shape giving improved print definition. These two benefits combine to help the solder paste printing process produce an adequate amount of solder paste in the correct position on the circuit board pads. Today,stencil aperture area ratios from 0.66 down to 0.40 are commonly used and make paste printing a challenge. This paper presents data on small area ratio printing for component designs including 01005 Imperial (0402 metric) and smaller 03015 metric and 0201 metric chip components and 0.3 mm and 0.4 mm pitch micro BGAs. The aperture area ratios studied range from 1.06 down to 0.30. The effects of nano-coatings are studied and compared to uncoated laser cut,fine grain steel stencils. Stencil thicknesses are varied from 0.003 inch (75 µm) to 0.004 inch (100 µm) and to 0.005 inch (125 µm). Solder paste powder size is varied including IPC Types 3,4 and 5. The effects of all of these variables are examined in relation to small aperture area ratios. Based on the results of the work a set of guidelines for stencil thickness,stencil nano-coating and solder paste type will be proposed in order to achieve good solder paste printing results.

As a surface finish for PCBs,Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) was selected over Electroless Nickel/Immersion Gold (ENIG) for CMOS image sensor applications with both surface mount technology (SMT) and gold ball bonding processes in mind based on the research available on-line. Challenges in the wire bonding process on ENEPIG with regards to bondability and other plating related issues are summarized. Gold ball bonding with 25um diameter wire was performed. Printed circuit boards (PCBs) were surface mounted prior to the wire bonding process with Pb-free solder paste with water soluble organic acid (OA) flux. The standard gold ball bonding process (ball / stitch bonds) was attempted during process development and pre-production stages,but this process was not stable enough for volume production due to variation in bondability within one batch and between PCB batches. This resulted in the standard gold ball bonding process being changed to stand-off-stitch bonding (SSB) or the ball-stitch-on-ball (BSOB) bonding process,in order to achieve gold ball bonding successfully on PCBs with an ENEPIG finish for volume production. Another area of concern was pad metal lifting (PML) experienced on some PCBs,and PCB batches,where the palladium (Pd) layer was completely separated from nickel (Ni) either during wire bonding or during sample destructive wire pull tests,indicating potential failures in the remainder of the batch. Evaluation of failed PCBs was performed using cross-section analysis,X-Ray Fluorescence (XRF),and Scanning Electron Microscopy (SEM)/Energy Dispersive x-ray Spectroscopy (EDS),which identified process issues,such as inclusions,or hyper corrosion which caused either localized or complete separation of the Pd from Ni layer. Through extensive investigation,using 8D and Kepner-Tregoe problem solving methods,solutions to the problem were discovered in the majority of cases,even though the exact root cause remained unclear due to multiple PCB manufacturing variables being changed at the same time.

Wire bonded packages using conventional copper leadframe have been used in industry for quite some time. The growth of portable and wireless products is driving the miniaturization of packages resulting in the development of many types of thin form factor packages and cost effective assembly processes. Proper optimization of wire bond parameters and machine settings are essential for good yields. Wire bond process can generate a variety of defects such as lifted bond,cracked metallization,poor intermetallic etc. NSOP – non-stick on pad is a defect in wire bonding which can affect front end assembly yields. In this condition,the imprint of the bond is left on the bond pad without the wire being attached. NSOP failures are costly as the entire device is rejected if there is one such failure on any bond pad. The paper presents some of the failure modes observed and the efforts to address NSOP reduction.

Portable electronics demand that inductors and transformers be implemented in low profile surface mount packages. In communication systems,magnetic components are used for impedance matching,voltage isolation,energy storage,noise filtering,and combining signals. Inductors can be implemented on ferrite bobbins with semi-automatic winding equipment. The inductance value and performance is constrained by the low inductance factor (AL) of the bobbins and resistance of the fine gauge wires used to construct the windings. RF transformers are usually wound on either ring or binocular shaped core structures. Small size defies automated winding and the majority of devices are wound manually using low cost labor. With manual construction there are issues with consistency and reliability. Embedded magnetics provides a new approach for fabricating the small transformers and inductors used in RF circuits. Ferrite elements are embedded into a FR-4 substrate and the device windings are realized using printed circuits techniques. This approach provides highly consistent performance and eliminates the need to dress fine wires and welding or soldering them to the package I/O pads. Additionally,the devices are fabricated in an automated and batch process. Rather than winding one at a time,devices are fabricated in a panel array format. With automation comes improved consistency and reliability. This paper describes the device composition and fabrication on a printed circuit line. A design example is presented to show the circuit layout and test results.

The electronics industry is experiencing a renaissance in semiconductor package technology. A growing number of innovative 3D package assembly methodologies have evolved to enable the electronics industry to maximize their products functionality. By integrating multiple die elements within a single package outline,product boards can be made significantly smaller than their forerunners and the shorter interconnect resulting from this effort has contributed to improving both electrical performance and functional capability. Multiple die packaging commonly utilizes some form of substrate interposer as a base. Assembly of semiconductor die onto a substrate is essentially the same as those used for standard I/C packaging in lead frames; however,substrate based IC packaging for 3D applications can adopt a wider range of materials and there are several alternative processes that may be used in their assembly. Companies that have already implemented some form of 3D package technology have found success in both stacked die and stacked package technology but these package methodologies cannot always meet the complexities of the newer generation of large-scale multiple function processors. A number of new semiconductor families are emerging that demand greater interconnect densities than possible with traditional organic substrate fabrication technology. Two alternative base materials have already evolved as more suitable for both current and future,very high-density package interposer applications; silicon and glass. Both materials,however,require adopting unique via formation and metallization methodologies. While the infrastructure for supplying the glass-based interposer is currently in development by a number of organizations,the silicon-based interposer supply infrastructure is already well established. This paper outlines both positive and negative aspects of current 3D package innovations and addresses the challenges facing adopters of silicon and glass based interposer fabrication. The material presented will also reference 3D packaging standards and recognize innovative technologies from a number of industry sources,roadmaps and market forecasts.

Traceability has grown from being a specialized need for certain safety critical segments of the industry,to now being a recognized value-add tool for the industry as a whole. The perception of traceability data collection however persists as being a burden that may provide value only when the most rare and disastrous of events take place. Disparate standards have evolved in the industry,mainly dictated by large OEM companies in the market create confusion,as a multitude of requirements and definitions proliferate. The intent of the IPC-1782 project is to bring the whole principle and perception of traceability up to date. Traceability,as defined in this standard will represent the most effective quality tool available,becoming an intrinsic part of best practice operations,with the encouragement of automated data collection from existing manufacturing systems,integrating quality,reliability,predictive (routine,preventative,and corrective) maintenance,throughput,manufacturing,engineering and supply-chain data,reducing cost of ownership as well as ensuring timeliness and accuracy all the way from a finished product back through to the initial materials and granular attributes about the processes along the way. Having the proper level of traceability will also help ensure counterfeit components do not end up in a product. Through effective policing in the use of any and all components,any material found to be counterfeit will be immediately traceable to source,and hence responsibility is assigned. IPC 1782 will work hand in glove with the U.S. Department of Defense’s current counterfeit component effort. The goal of this project is to create a single flexible data structure that can be adopted for all levels of traceability that are required across the industry. The scope includes support for the most demanding instances for detail and integrity such as those required by critical safety systems,all the way through to situations where only basic traceability,such as for simple consumer products. A key driver for the adoption of the standard is the ability to find a relevant and achievable level of traceability that exactly meets the requirement following risk assessment of the business. The wealth of data accessible from traceability for analysis can yield information that can raise expectations of very significant quality and performance improvements,as well as providing the necessary protection against the costs of issues in the market. Taking a graduated approach will enable this standard to succeed where other efforts have failed.

With technology these days,we often find solutions without a problem,rather than the other way around. The concept of the “Internet of Manufacturing” (IoM),combined with the evolution toward automated and computerized factories,is an exciting subject for engineers. However,managers who are responsible for the business side of manufacturing,need a solid business case for change that is driven either by need from the customer or by a compelling internal performance enhancement. The decision to purchase new equipment today is a catch-22 — with requirements to be “future-proof” just in case the factory will become a computerized operation as put forward by the proponents of Industry 4.0,but without really knowing the full implication of what that might be. Let us take a look at these two potential business cases. First,we will look at the likely reasons that would compel customers to change their demands and requirements from factories,whether OEM or EMS. Second,we will look at what is the “state of the art” today for automated factories that have a controlling layer of computerization,understand the challenges and potential costs,as well as direct operational benefits. We will see if we can find the balance point between the two. Lastly,we will look forward at what needs to be done to provide a practical and economical way to address the various challenges to implementing an Internet of Manufacturing,with solutions and benefits for both manufacturers and customers. If these areas are addressed,the adoption of computerization and the creation of more automated factories could then become mainstream.