Many companies use “one stop testing” as a solution to the test issues in a manufacturing environment rather than discrete
“islands of test”. Low volume,high mix electronic manufactures are concerned about floor space,which can be expensive.
As well as operator training,which can be considerable if a separate test solution is used for each product manufactured.
Very high volume manufacturers can also benefit from a single stage electrical test solution if the test times are less than the
beat rate of the line. This is especially true if the system in fully automated. As with low volume manufacturers floor space
and operator training costs can be reduced,but the significant saving is in early defect detection that helps reduce scrap rates
and improves line efficiency.
By combining electrical test into one system and having the system directly integrated into the production line,the system
can detect defect at the earliest stage of the board manufacture. As a base,incircuit test (ICT) is a well-established electrical
test technique and has been used successfully for a number of years and has a long history of being integrated into the
production line. PXI has established itself as the standard for cost effective integrating of functional instruments into a test
system. By combining ICT and PXI into one solution,it can perform incircuit test,help overcome ICT access issues and
perform functional tests. This universal test solution provides a smaller footprint,consistent operator interface and overall a
lower cost of test.
This paper will discuss the advantages of a universal integrated electrical test solution,at the normal Incircuit Test stage of
production,to minimize production costs and help improve product quality using two case studies. One is a low volume
high mix manufacturer and the other a high volume automotive electronics manufacturer.

The physical mechanisms behind tin whisker formation in pure tin (Sn) films continue to elude the microelectronics industry. Despite modest advances in whisker mitigation techniques (i.e.,barrier metal underlayers,substrate/film annealing,etc.) and encapsulation,ways to fundamentally prevent whiskers from forming remain unknown. It has been said that tin plating thicknesses of <0.5 um or >20um are “whisker inhibiting”[3,6]. In the case of the former claim,it may be argued that as film grains approach an equiaxed proportion (i.e.,the average columnar grain height is roughly equivalent to the average grain diameter),stress compensation is no longer preferential to the normal direction with respect to the plated film. Grain morphology has often been pointed to in the literature as a likely factor in Sn whisker formation due to the fact that SnPb,which does not whisker,has equiaxed grains while pure Sn exhibits columnar grain growth,which is only equiaxed when the film thickness matches the average grain diameter. Our work examines the effect of adding grain refiners during tin electroplating,with particular focus on the ‘as-deposited’ film morphology and the associated incidence of whiskering. We have included polycrystalline Sn ‘control samples’ in our study,and as an extension of our previous work[1],we have compared the structure and whiskering incidence of nanotexturized Sn on both polycrystalline and nanocrystalline Cu underlayers.

Compliant press-fit zones apply external mechanical stress to copper and tin surfaces of plated through holes at printed circuit boards during and after performing the press-in process. This external pressure increases the tendency to create tin whiskers. These whiskers grow on much shorter time scales than whiskers caused by strain introduced by intermetallic phase growth. Also the length of these whiskers can exceed 2 mm under special circumstances and cause malfunction of electronic circuits. The results shown in this paper support the understanding for the growth mechanisms at different geometrical shapes of press-fit zones and therefore give strong impact on the risk analysis.

Twenty-nine different cells phones have been disassembled,ground up,dissolved and analyzed for elemental content,mainly for information about the metals present in the phones,but also for some metalloids and non-metals. The following elements were detected in some or all of the phones: Be,Mg,Ti,V,Mn,Fe,Co,Ni,Cu,Zn,As,Nb,Ag,Sn,Sb,Ba,Ta,W,Au and Pb. The following elements were not detected: Se,Cd,In,Te,Pt,Tl or Bi. The paper will discuss the method used and propose possible sources in the telephones for certain elements of interest and the reasons for the interest in some of the elements.

Pure tin is a common finish for copper hook up wire,coaxial cable,ground braid and harness assemblies used on electronic assemblies. Historically there have been fewer reports of whisker growth on tin coated copper wire than on other types of tin coated parts. This paper presents data from humidity- temperature conditioning and electron microscopy inspection of tin coated wire specimens of various size and age. After 4000 hours of 85°C/85%RH conditioning,some of the wires showed tin whisker growth,but the growth was very sparse with near zero density distribution and whisker lengths were typically less than 10 microns. The data indicate very low risk for whisker growth on tin coated copper wire,braid and cable.

- Live Cycle Assessment
- Early Product Analysis / “DFX” Challenge
- Keys to Scaling #1: Processes and Systems
- Systems can Extend “Traditional” LCA
- Keys to Scaling #2: Data Exchange Standards
- Leveraging Environmental Compliance Practices
- Using Systems + Standards: A Proven Approach
- IPC-175x Data Exchange Standards
- 175x Example (snippet) – Machine Readable
- Current 175x Limitations (Relative to LCA needs)
- 175x Opportunities for LCA

Companies that have initiated internal resources to obtain compliance data have realized that collecting,and more importantly,maintaining the currency of that data requires more resources than available. For a case in point,one such company utilized 3 component engineers over 3 years to collect compliance data on ~5000 parts only to find out that all the data collected was now out of date. Why was it out of date? Among several reasons: the EU changed the method for reporting exemptions,REACH SVHC’s were added (several times) and manufacturers were forced to change and republish their declaration documents to meet these new requirements. Additionally,in North America Conflict Minerals declaration has been introduced demanding yet more documentation collection and maintenance. And,there will be more change.
Compounding the resource need is a lack of standardized data. All manufacturers publish in pdf,Excel,Word docs,etc,where there is no normalized standard. The data needs to be “lifted” from these documents and transferred to a parsed database. Quality and accuracy is at risk both from the supplier (~40% of supplier declaration documents are currently being returned to the manufacturer for correction) and the manual transfer process itself. Additional resources are needed in QA personnel with a specialized expertise in Environmental Compliance.
A centralized,publicly available database would be ideal if there were a method of ensuring quality of data served,however getting the industry to adopt a standard has not been possible. There are opt-in web services that require the manufacturer to normalize and upload data to a portal; however there is no quality control and no guarantee that all suppliers will participate leaving the need,once again for dedicated internal resources to provide specialized QA/CE collection and maintenance personnel.
A study was conducted to determine what internal resources would be needed to accurately collect,QA maintain and produce product level compliance reports on ~5000 components and material. Here is a list of the findings:
• 3-5 technicians to find and manually transfer the data from manufacturers published documents
• 2 component engineers to review and QA the physical characteristics of the data collected
• 2 Environmental compliance engineers to review,QA and manage the correction phase
• Database software
• IT implementation resources
Most companies do not have or can’t afford this reality. Since the manufacturers are not likely to adopt a standard method for publishing in the near term,and more change is inevitable,the only solution available today is a 3rd party data provider; one that does have the resources to collect,QA,maintain and deliver. Our study found that the fees for these 3rd party services are typically less than the cost to implement the necessary resources internally. Other IPC members can attest to this and their success.

The new plasma polymer PCB final finish that eliminates harsh chemicals and waste streams also promises to eliminate creep corrosion,but will it stand the test of time? Before any new product or process can be implemented,it must be tested extensively to demonstrate its fitness for use. Performance from the beginning to end of the product life cycle must be measured or simulated. For the new PCB finish,the gamut of testing included characterizing the application process,storage robustness,corrosion resistance,solderability and joint reliability. Methods used to test the coating included FTIR,EDX,mixed flowing gas,steam aging,wetting balance,thermal aging,shear testing,and micro sectioning with both SEM and optical microscopy. Over a year’s worth of testing performed by two independent US laboratories is presented in this paper. It details the purpose,method and results of each test and discusses the findings with respect to long-term performance.

Modern electronics typically consist of microprocessors and other complex integrated circuits (ICs) such as FPGAs,ADCs,and memory. They are susceptible to electrical,mechanical and thermal modes of failure like other components on a printed circuit board,but due to their materials,complexity and roles within a circuit,accurately predicting a failure rate has become difficult,if not impossible. Development of these critical components has conformed to Moore's Law,where the number of transistors on a die doubles approximately every two years. This trend has been successfully followed over the last two decades through reduction in transistor sizes creating faster,smaller ICs with greatly reduced power dissipation. Although this is great news for developers of high performance equipment,including consumer products and analytical instrumentation,a crucial,yet underlying reliability risk has emerged. Semiconductor failure mechanisms which are far worse at these minute feature sizes (tens of nanometers) result in higher failure rates,shorter device lifetimes and unanticipated,early device wear out.
Physics-of-Failure (PoF) knowledge and an accurate mathematical approach which utilizes semiconductor formulae,industry accepted failure mechanism models,and device functionality can access reliability of those integrated circuits vital to system stability. Currently,four semiconductor failure mechanisms that exist in silicon-based ICs are analyzed: Electromigration,Time Dependent Dielectric Breakdown,Hot Carrier Injection and Negative Bias Temperature Instability. Mitigation of these inherent failure mechanisms,including those considered wear out,is only possible when reliability can be quantitatively calculated. Algorithms have been folded into a software application to not only calculate a failure rate,but also give confidence intervals and produce a lifetime curve,using both steady state and wear out failure rates,for the integrated circuit under analysis. Furthermore,the algorithms have been statistically verified through testing,employ data and formulae from semiconductor materials (to include technology node parameters),circuit fundamentals,transistor behavior,circuit design and fabrication processes. Initial development has yielded a user friendly software module with the ability to address silicon-based integrated circuits of the 130 and 90nm technology nodes.
DfR is now working to extend the capability of the tool into smaller technology nodes (65nm and 45nm) and other material sets such as silicon on insulator (SOI). Several commercial organizations have indicated a willingness to assist with the development and validation of 45nm technology through integrated circuit test components and acquisition of field failure data. Continued development would incorporate this information and would expand into functional groups relevant for analog and processor based integrated circuits.
The initial work was performed by DfR Solutions,and funded by Aero Engine Controls,Boeing,GE,NASA,DoD,and FAA in cooperation with the Aerospace Vehicle Systems Institute (AVSI).

Continental is using the IPC solder spread coupon (adopted from NPL) to evaluate Pb-free solder pastes and PCB surface finishes for Solderability. This presentation will compare and contrast solder spread results for multiple PCB finishes using multiple Pb-free solder pastes. The spread data is collected for as-received PCBs and after one or more reflow processes to observe the degradation in spread for the different surface finishes. Very different behavior is observed when comparing common Pb-free compatible PCB surface finishes such as ENIG,OSP and immersion tin. Efforts to define specific pass/fail criteria for the solder spread coupon,based on comparisons to other common criteria,will be included. Additional information on the impact of variations in solder paste print volume to the resulting spread performance may also be presented if time/space allows. An overview of the results of the IPC 4-14 ENEPIG solder spread results may also be included if agreed to by the 4-14 committee.