Although many of the QFN and bottom termination products are small in outline and utilize a plastic encapsulated copper
lead-frame structure they do not resemble the more traditional small outline (SOIC) lead-frame packaged semiconductors
because the termination features do not extend beyond the package edge. Many of the QFN packages have an exposed die
attach pad (DAP) feature on the package bottom surface to provide a more direct thermal interface with the mating circuit board surface. Since there is no protruding lead on the package and DAP features are relatively large,solder defects are often beyond acceptable levels.
Key issue: Because the DAP feature can be rather large,printing solder paste with a matching outline can result in uneven solder distribution during the assembly process. This uneven solder distribution causes the parts to tilt,often causing solder bridging and/or disconnect of the perimeter located terminal contacts.
Solution: To compensate for this condition and potentially reduce solder defects,unique DAP print pattern variations can be adopted. Optimizing the solder stencil pattern will ensure that the package bottom surface remains parallel with the circuit board surface during the reflow solder attachment process.
In this paper we will review a wide range of plastic encased no-lead package configurations,industry package standards,and terminal design variations as well as defining the criteria for land pattern design and solder paste stencil development and assembly process methodologies detailed in the new IPC-7093 standard,“Design and Assembly Process Implementation for Bottom Termination Components”.

The CAD library is the starting point that affects every process from PCB layout through PCB manufacturing and assembly. There are dozens of things to consider when creating a CAD library that are often overlooked or not even considered that will directly affect the quality of the part placement,via fanout,trace routing,post processing,fabrication and assembly processes. Part 1 of this paper describes every aspect that should be considered when creating chip CAD library parts and the impact that each feature of the CAD library has in the PCB process.

This paper details the results achieved by the High Density Packaging Users Group (HDPUG) Consortium investigating the hole-wall to hole-wall CAF performance of 20 different Pb-free printed wiring board materials in 20 layer constructions. Seven of the materials are investigated with 2 different 20 layer constructions (different glass styles and resin contents) for a total of 27 different builds. The materials are tested both as built and after Pb-free Reflow at 6x 260C. Materials in the test include high Tg,filled FR4 materials,high Tg halogen free FR4 materials,and high speed materials. Data is presented showing the impact of reflow,the impact of glass styles on the materials and some unexpected CAF results as well.

The propensity of printed circuit boards to electrochemical migration has been assessed traditionally by using surface insulation resistance technique with a DC bias on standard comb structures. Different from this,an AC impedance measurement has been used to evaluate the kinetics of electrochemical migration process and provide detailed information about cell parameters such as solution resistance,charge transfer resistance,and double layer charging capacitance during dendritic growth. The solution resistance and charge transfer resistance decreased during the dendritic growth,while the double layer charging capacitance showed an oscillating nature. The dramatic changes of these parameters due to dendritic growth may be used as forerunner signals prior to dendritic growth and developed as a prognosis technique. A physicochemical model was fitted into the experimental results and a simulation was conducted. The simulation results confirmed the experimental data.

Pad cratering refers to the initiation and propagation of fine cracks beneath BGA pads in organic substrates or printed circuit boards. These cracks,which usually initiate under the application of excessive mechanical loads,represent a serious reliability concern for the industry. In typical board level reliability tests,solder joint failures are detected by an increase in electrical resistance of a daisy chain circuit followed by failure analysis. However,board level testing to determine the onset of BGA pad cratering has been problematic because the early stage of this failure mode is not associated with an electrical signature. Based on the mechanism of pad cratering,it is known that the cracks initiate beneath BGA pads and grow under continually increasing stresses until the pad completely separates from the substrate and a pad “crater” is formed. The catastrophic fracture of an interconnect,which causes an electrical “open”,is in fact the final and most catastrophic stage of the failure. At present the higher strain levels based on electrical resistance monitoring are being reported and used in design practices.
In this study,a new monitoring approach based on acoustic emission has been introduced for early detection of pad cratering failure. Two different lead-free daisy chain test vehicles were used with 1.0 mm pitch HSBGA-1096 and 0.8 mm pitch CABGA-160 packages,and four-point bend tests were performed to induce pad cratering. Acoustic emission activity from the test vehicles was monitored along with the electrical resistance of the daisy chain circuit. The bend test results,in conjunction with failure analysis,have shown that acoustic emission monitoring is indeed an effective methodology to detect the onset of the pad cratering. In contrast,the electrical daisy chain failure was detected at significantly higher strain. Using the acoustic emission approach,it has been found that PCB pad cratering failures can initiate at strain levels significantly lower than previously reported. This board level test methodology may now be used to evaluate the propensity of different materials and packages to pad cratering,and also to improve back-end manufacturing processes without using daisy chain test vehicles.

Surface mount area arrays (SMAA) have been in existence for decades and are increasingly becoming more important as printed circuit board (PCB) assemblies become further complex with package miniaturization and density. Although the PCB space savings afforded with SMAA solder joint technology is advantageous and necessary it is also extremely important that the solder joints formed when using SMAA technology are reliable and robust. A recent advancement in SMAA technology is the solder charge grid array (SCGA). During the development of this new SMAA technology much attention was giving to existing SMAA structures such as the ball grid array (BGA) and column grid array (CGA) with the intent of improving on some of the advantages afforded by each of these technologies. A focus was placed on improvements in the areas of processing,inspection and reliability while maintaining the strengths of existing SMAA features such as density,simplicity and cost. As a result,SCGA technology requires no special processing or equipment during PCB assembly and has been designed to be flexible enough to be used as a drop in replacement for existing BGA or CGA components. SCGA also improves on the co-planarity,inspection,compliancy,and reliability challenges of current SMAA solder joint attachment technologies. This paper will focus on two primary areas of the SCGA: the design and research involved in the development of the SCGA,and the reliability testing completed to insure the SCGA meets industry specifications for SMAA technology and to predict the performance of the SCGA through harsh environments.

As Original Design Manufacturers (ODM) adopt the use of finer pitch connectors,with increased pin count on PCB assemblies. It becomes challenging for Electronic Contract Manufacturing Services (EMS) to build with very low or zero defects in the Printed Circuit Board Assembly (PCBA) operations.
In this paper we will share our experiments for improving the SMT process with these connector types: 1. Samtec’s SEARAYTM (AEAM/AEAF Series) connectors with 500 leads which have a unique solder charge design. The leads themselves are on a 50 x 50 mils pitch from row to row. 2. Two Press-fit SFP Cages with different lead lengths,1 with protrusion and 1 with no lead protrusion on an 18 layer fab (2.5mm thickness).
Case1. Samtec’s SEARAYTM (AEAM/AEAF Series) connector
The connector leads have a solder charge (pre-tin),and the minimum stencil thickness requirement is 6 mils. However the assembly supports a mixture of component technology for this product,where many components need the use of a 4 mils stencil thickness. The fab thickness is 40 mils. There are two main SMT process improvements which we did to eliminate defects: 1. Use 6 mils stencil thickness with a Step-Down to support the 4 mils thickness requirement of other components on the assembly,and replaced the use of a Mini-stencil for the connectors to solve operator handling issue that have been causing damage to the solder charge and others; 2. Based on experimental data,we also adjust the profile for optimization of the solder joints of the connector. With new stencil and oven profile,the defects reduced from 15% to < 0.5% for the connector.
Case2. Two Press-fit SFP cages with different lead lengths
Because there were issues with these Press-fit SFP cages failing mechanical drop test. The customer requested us to add solder to the peripheral row of pins of the SFP cages,for a stronger retention to the fab. We couldn’t make all pins have a good solder joint with a Non-modified wave fixture,and wave as a normal process. Therefore,we have new process designs (a. Modified wave fixture,add flux on the top side of PCB,and wave as a normal process for the 2 different vendor’s components; b. A non-modified wave fixture and add flux on the top side of PCB and wave as a normal process; c. Modified wave fixture and wave as normal process). All these Selective Wave process methods are working: these cages now have good retention with the fab,passing mechanical drop test,and no defective pins for current boards were building. We use 2DX with tilting angle detector to check the solder joints of the cages.
We used 2DX machine to identify boards with critical connectors by optimized method.

With the predominance of no-clean soldering processes and ever decreasing component standoff,the industry has had to consider the reliability of,what may be,partially activated or “gooey” flux residues under component bodies. Similarly,questions have also risen about the reliability of flux residues resulting from the reflow of no-clean solder pastes that are “entrapped” under RF shields or “cans”,where escape of the volatile ingredients of the flux is greatly hindered. In this paper,discussion will be made regarding an experiment designed to mimic the aforementioned conditions and how these conditions affected the SIR performance of the no-clean flux residues. A variety of no-clean solder paste flux residues will be discussed,including a halogen-containing,Pb-free solder paste flux; a halogen-free,Pb-free solder paste flux; a halogen-free,Pb-free solder paste flux with a residue optimized for pin probing; and a halogen free SnPb solder paste flux.

Convection soldering remains the most common reflow process in electronic assembly,mostly in air,but sometimes using a nitrogen atmosphere to reduce oxidation.
On the other hand,vapor phase soldering remains a niche market: it has been dedicated for years for use on complex boards with heavy mass and/or a large mix of component sizes. Despite its excellent heat transfer capabilities and high wetting performance,this process suffered from weaknesses that prevented it from being used on a large scale: high fluid consumption (CFCs),high tombstoning effect,long process time,and the inability to integrate it into a production line.
In the last few years,vapor phase reflow technology has been improved: New fluids,with boiling temperatures up to 240°C,have been developed,the consumptions have been greatly reduced and the control of preheat and peak ramp rate has been improved,lowering the tombstoning effect.
With lead-free implementation,some limitations are observed on complex boards with convection ovens: the thermal reflow process window is reduced due to the higher temperatures required for SAC alloys,the maximum temperature allowed for fragile components,and the wide range of component sizes.
Vapor phase reflow might be an option to consider.
However,because of the relatively low peak temperatures and the elimination of oxidation with this process,a question may arise about the reliability of the paste residue. More unburned activators might remain on the board,which could cause some corrosion to develop,even when using no-clean solder pastes.
The purpose of this paper is to assess the reliability of several lead-free,no-clean paste residues after vapor phase reflow in comparison to convection reflow. We will use Surface Insulation Resistance (SIR) and Electrochemical Migration (ECM) according to IPC standards,in addition to the Bono test which has been proven to better differentiate the nature of solder pastes residues.

Electroplated Ni/Au over Cu is a popular metallization for PCB finish as well as for component leads,especially wire-bondable high frequency packages,where the gold thickness requirement for wire bonding is high. The general understanding is that less than 3 wt% of Au is acceptable in SnPb solder joints. However,little is known about the effect of Au content on the reliability of SnAgCu solder joints. The purpose of this study is to determine the acceptable level of Au in SAC305 solder joints. Three different package platforms with different Au thicknesses were assembled on boards with two different Au thicknesses using a standard surface mount assembly line in a realistic production environment. The assembled boards were divided into three groups: as-built,isothermally aged at 125°C for 30 days,and isothermally aged at 125°C for 56 days. All boards were then subjected to accelerated mechanical reliability tests including random vibration and drop testing. The results show that solder joints with over 10 wt% Au are unacceptable. If Cu is available to dissolve in the solder joint,then an Au content under 5 wt% will not significantly degrade the reliability of the solder joint. When Ni layers are present on both the board and component sides of the interface,this limits the ability of Cu to dissolve into the solder joint and hence an Au content under 3 wt% is acceptable. The failure mechanism for solder joints with high Au content is fractures through the AuSn4 IMC. Our comprehensive long-term reliability study did not confirm the finding by Ho et al. (2002) that the weak interface between (Au,Ni)Sn4 and Ni3Sn4 results in brittle interfacial failure. Additional findings confirmed the danger of placing parts near high stress areas and that a high level of voiding reduced reliability.