This paper addresses the effect of pulse plating of electronic interconnects for advanced electronic modules. This paper
builds on earlier work by correlating plating cell and tank design issues and tank characterization studies with standard
mechanical and reliability tests. The current work evaluates the resulting copper deposits in terms of throwing power,
mechanical and reliability tests and compares the results to a current state-of-the-art process. The present work relies on
electrical mediation for a highly controlled electrodeposition process that results in a very uniform and reproducible deposit;
selection of the electric mediation parameters is based on considerations of mass transfer as well as microprofiles and
macroprofiles related to current distribution. Data for plating industry test panels containing PTHs of approximately 5:1,
10:1,and 15:1 aspect ratios are presented. Using a pulse waveform sequence,throwing powers of approximately 90-100%
are observed at plating rates of approximately 20 ASF.

Nanocrystalline and ultra-fine grain copper can potentially offer increased reliability and functionality of printed wiring
boards due to expected enhancements in strength and achievable wiring density by grain size reduction. In this research inhouse
synthesized nanocrystalline and ultra-fine grain-size copper foils produced by pulsed electrodeposition were compared
with commercially available electronic grade polycrystalline electrodeposited (EG-ED) and cold rolled annealed (EG-CRA)
copper foil. The microstructures of all materials were characterized by transmission electron microscopy (TEM). Nanoindentation
and the four-point probe technique were used to evaluate their hardness and electrical resistivity,respectively. It
is shown that grain size reduction results in significant increases in hardness at a moderate loss in conductivity.

Continuous measling,or unidirectional crazing,was observed in a multi-layer polyimide printed wiring board following
assembly operations. Damage to the PWB preferentially followed the warp direction of the glass fiber reinforcement and
extended beyond the region of localized heating. Further investigation revealed that glass fiber pullout in cross-sectional
mounts is an indicator of laminate material that is prone to measling or crazing. Testing showed that boards with fiber pullout
were significantly more likely to show damage in base material in subsequent process,especially when a drying bake was not
recently performed. Damage to these PWBs consisted of cracks not between bundles of glass-fiber reinforcement,but within
individual bundles. These cracks may produce reliability risks in PWB.

Today both Interconnect Stress Test (IST) and Highly Accelerated Thermal Shock (HATS) test methods are used to measure
plated through hole via reliability. Both of these test methods have proved useful in their ability to quantify via reliability
and have gained a wide level of acceptance and credibility within the industry.
This paper covers the use of HATS testing to determine the long-term reliability impact of simulated higher temperature
assembly and rework thermal excursions. In particular,this paper will present data showing a complex relationship between
higher temperature assembly processing and rework cycles,and subsequent HATS and IST cycles to failure (CTF). The
Inverse Power Law (IPL) will be used to plot the via stress versus CTF relationship when cycling below the laminate material
glass transition temperature (Tg).

The surface finishes Ni-P/Pd/Au (hereafter referred to ENEPIG) and Ni-P/Au (hereafter referred to ENIG) were
prepared on ball grid array (BGA) circuit boards by electroless/immersion plating method. The IMCs (Inter metallic
compounds) of Sn37Pb and Sn3.0Ag0.5Cu solder with these finishes were compared using TEM (Transmission
Electron Microscope). It was found that the IMC crystal lattice is dependant on solder material and the solder joint
reliability is dependant on both the solder material as well as the surface finish. In using Sn3.0Ag0.5Cu solder,the Pd
in the ENEPIG finish limits the Ni diffusion and exhibits excellent solder joint reliability. In the combination of Sn/Pb
solder and ENEPIG,the Ni diffusion is accelerated and solder joint reliably is compromised.

Over the past ten years,two new test methods: Interconnect Stress Test [1] and Highly Accelerated Thermal Shock [2] have
been developed to perform thermal cycling testing and in particular,to measure plated through hole reliability. Both of these
test methods have proved useful in their ability to quantify plated through hole reliability and have gained a wide level of
acceptance and creditability within the industry. Along with more tradition air-to-air and liquid-to-liquid thermal cycle
methods,these two new test methods expand the test methods available to the interconnect industry. While the number of
testing options for plated through hole thermal cycling has increased,there has been little work performed within the industry
on developing methods to analyze and use the data coming from these new test methods.
This paper covers use of IST testing to obtain plated through hole cycle to failure data followed by methods to analyze and
plot the data over a wide range of temperatures. In particular,the paper will focus on the use of material properties like the
modulus as a function of temperature and the coefficient of thermal expansion as a function of temperature to calculate the
stress on a plated through hole versus temperature. In this paper we will also explore the use of the Inverse Power Law (IPL)
to analyze the plated through hole stress versus cycle to failure relationship. Once we have used IPL to established the cycle
to failure relationship to stress for a given laminate and PCB design,it is then possible to estimate the number of cycles to
failure in the field as a function of the number of cycles of assembly stress,the peak assembly temperature,and the maximum
temperature in the field.

Volume electronic manufacturing environments are constantly seeking solutions to bottlenecks at end-of-line test.
Bottlenecks are being seen increasingly on high volume automotive,telecomm & consumer electronic product lines where
assembly beat rates are much faster than that of the test processes. Manufacturing engineering teams have few available
solutions that can maintain test coverage and not increase the unit cost of test. Until recently the only viable solution required
replicating the test platforms to gain more capacity to deal with the higher volume demand. This solution consumed more
floor space,capital budget,operators & maintenance time. New solutions using concurrent test techniques promise to unblock
the test bottleneck by maximizing the test platform asset utilization across multiple units under test simultaneously.
Electronics evolutions and revolutions – whether in component technology or in the products in which they are used –
continue across the globe. While the world awaits the next electronic must-have marvel like the PC or the cell phone,the
evolution and continual re-engineering of existing consumer,commercial and aerospace products is as fast-paced as ever.
Electronics manufacturers continue their quest for products that provide greater functionality and consume less power,
typically in packaging that gets smaller and smaller.
As a result of this continual evolution,new technologies and trends in the production of printed circuit boards are required,
presenting new challenges for how PCBs are built and tested.

Selecting an optimal test strategy is a complex task today. There are many test inspection and test methods available. The
most common choices to find manufacturing defects on printed circuit boards are manual visual inspection (MVI),solder
paste inspection (SPI),automatic optical inspection (AOI),automatic x-ray inspection (AXI),in-circuit test (ICT),and
functional test (FT). This paper presents the key attributes to consider when designing a test strategy selection tool and how
such a tool should work. Among the key attributes when selecting an optimal test strategy are: defect spectrum and defect
levels,where in the manufacturing process defects are introduced,different test and inspection systems’ test effectiveness,
cost of test and inspection systems including programming and fixturing,cost of finding defects at different stages in the
manufacturing process or in the field,and of course the complexity of the printed circuit board. Outputs from the tool should
include yield calculations,DPMO (Defects Per Million Opportunities) at different stages of the manufacturing process,cost
impacts,and defects captured and defects escaping. These predictions should be made for the different test strategies
selected for analysis. The paper will describe how such a Test Strategy Tool can be design and also results in using a tool
described in the paper.

In these days of high mix low volume there is increasing pressure on the SMT departments of manufacturing companies to
reduce changeover times and increase machinery utilization. An enormous effort has been taken within the SMT,Production
Engineering and QA departments to ensure the setup of pick and place machines are accurate,and still issues of incorrect
parts loaded onto PCB’s exist. Each time this seemingly random event occurs there is enormous speculation as to how it
happened and generally an additional control is concocted to supposedly correct this from “ever happening again”. All this
has done is added more wasted time in the changeover of each job on the SMT line.
What needs to happen is an entire re-think of the process of SMT line changeover and to use technology to assist and
streamline this process. First Article Inspection Machines are available to ensure that incorrect set-ups are a thing of the past
as well as speeding up the entire process so that the downtime on your expensive SMT lines is kept to a minimum. This study
has been done in order to compare the standard manual processes used in normal CEM environments to the automated First
Article Inspection (FAI) System assisted methods and the results are presented here.
In order to fully understand the process improvement aspects of the First Article Inspection System assisted methods a
comparison of both processes is detailed below that highlight the drawbacks as well as the areas that are improved.

In response to RoHS and other international environmental legislation,the semiconductor industry is moving toward the
elimination of lead (Pb) from packages. During the transitional period,both leaded and lead-free components coexist with
tin-lead and lead-free soldering processes. The compatibility of lead-free area array packages with tin-lead soldering
processes is a critical issue if the transition becomes prolonged as several product categories may take advantage of the
exemptions and continue to be built with tin-lead solder for some time to come.
The issue of “backward compatibility” arises because for BGA packages,the contribution of solder balls to the solder joint
material is very high (typically of 70% to 80%),and the assembly of lead-free BGA packages with tin-lead paste becomes a
major concern from the perspective of solder joint metallurgical uniformity and reliability.
In this study,the solder joint metallurgy of mixed alloys was characterized,and the amount of mixing of Pb through the
solder joint was analyzed,for different package types and under various process conditions. The results showed that the
solder paste amount (ultimately tin (Sn) percentage in the alloy) and the reflow temperature play critical roles in the mixed
alloy assembly,both in terms of compositional homogeneity and voiding. Homogeneous solder joints were seen at various
reflow temperatures ranging from 210°C to 230°C,depending on the Sn percentage in the mixed solder alloy. This study
will shed some light on the process optimization for backward compatible assemblies in order to improve yield and to create
more reliable solder joints.