A unified European roadmap for PWBs does not exist today. It is also most unlikely that a unified roadmap will available in a
foreseeable future time. However,the EIPC has worked together with many European companies and association to define
trends in technology based on the future needs of the industry. This paper will report on some of the trends that are included
in European company roadmaps and the HotCar project. More details have been documented in the European Technology
and Trend Report that has been put together by the German GMM VDE/VDI,the DGO,FED,ZVEI,the EITI as well as the
European Institute of Printed Circuit Boards. Leading companies involved in design of electronic equipment supported this
report. Also PCB fabricators,PCB assemblers as well as materials suppliers for PWBs and companies that develop latest
fabrication methods used to manufacture state-of-the-art electronic equipment. This paper will provide a snap shot on
developments that will impact the European Roadmap for PCBs and will help to guide electronic engineers to select the new
PCB technologies for advanced electronic devices.

Japan has a long history of publishing very important technology roadmaps. Some of the Japanese roadmaps published in the
past are:
JPCA Roadmaps
Report on the Technology Roadmap for Advanced Systems Integration and Packaging English version 1998,translated by IPC.What Makes Dreams Come True? A roadmap of microvia technology published in 1998 JIEP Roadmaps
The Technology Roadmap for Electronic Packaging Technology in Japan (1999 – 2010) English version September 1998,translated by SEMI EIAJ / (JIETA – Japan Electronics and Information Technology Industries Association) Report on Semiconductor Packaging Technologies,December 1996
Multi Media Vision 2005,March 1997 Report on MCM / KND Packaging Technologies,October 1997 In 1999 Japanese technologists decided to go to “JISSO”. JISSO is a made up word that means the total system integration. It
encompasses all relevant technologies,such as semiconductor ICs and their packages,other electronic components,PWB,materials,interconnecting structures,environmental protection,and system design.
This was a major decision on the part of the Japanese technology organizations. In 1999 and again in 2001 and 2003 there
has been a JISSO technology roadmap.
The first JISSO roadmap was published in 1999. The Japanese version was published in August 1999 and an English version followed in September 2000. The second JISSO roadmap was then published in April of 2001. This roadmap was also published in English. The 2003 JISSO roadmap was only published in Japanese.

With the objective of developing high thermal conductive laminates capable of being used as high current-carrying wiring
boards for automotive and industrial applications,we identified the optimum blending method and optimum fillers for
biphenyl-type epoxy resin that possesses high thermal conductivity,and studied laminating conditions. As a result,we
established a method to achieve homogeneous dispersion and we manufactured prepregs that are devoid of coating
irregularities. In addition,we found fillers capable of achieving a maximum thermal conductivity of 7.5 W/m·K and thereby
enhanced both thermal conductivity and insulation resistance. Although copper-foil peel strength was reduced,we increased
its strength by means of the roughening of rolled copper. In addition,we were able to determine molding conditions such as
press temperature.

Recent increasing demand for miniaturization and multi-functionality of electronic devices has lead to higher PWBs circuit
density design,requiring thinner insulation layers,smaller via holes and finer wiring lines than ever before. So that the
prepregs used to compose PWBs require better drilling ability and higher insulation reliability in additions to the demands of
thinner fabric. To meet these requirements,ASAHI-SCHWEBEL has developed a new type of ultra-thin prepreg capable of
forming as thin as 20µm thick single insulation layer by using 10µm thick glass fabric obtained by our proprietary uniform
glass fabric spreading method. Furthermore,we have succeeded to render UV-YAG laser drilling ability to resin/glass fabric
prepregs without impairing problematic hole-to- hole insulation reliability by chemically finishing the glass fabric with
inorganic nano-particles. The values achieved are 50µm via hole capability and no failure after 350 hours at 121?,85RH%
under 5 volts applied with hole -to- hole length of less than 150µm. The mechanical properties of the developed prepregs,
especially rigidity and dimensional stability,are found to be much better than those of other organic substrates. We believe
that this new type of prepreg is best suited for not only current but also future PWBs material,such as for buried capacitor
laminates containing high dielectric constant compounds.

A recent trend of increasing circuit density,particularly in the areas of plastic packages and multi-layer boards,has resulted in
ceaseless demand of improved mechanical properties for laminates with improved quality and reduced cost. In general,
mechanical properties of laminates composed of glass fabrics and thermosetting resin are strongly dependent on the resin
shrinkage during thermal cure,asymmetrical structure of the laminates and inhomogeneous structure of the glass fabric made
by glass yarns having twist,a presumably main cause of internal strain in the glass fabrics. We conducted in depth studies
intended to correlate the characteristics of glass fabrics to the mechanical performance of laminates,and have succeeded in
developing new glass fabrics using zero twist yarn. We have combined it with our uniquely developed “MS process”,by
which a homogeneous distribution of glass fibers in the laminates can be obtained quite easily. Eliminating internal strain by
use of twist-free yarn and MS process,these new laminates have proved not only to reduce warp and twist by as much as
50% compared to conventional laminates,but also to improve mechanical properties such as dimensional stability with low
standard deviation and C.T.E. by ca. 2ppm. In addition,the new laminates have exhibited excellent micro-diameter drilling
capability,such as laser drilling and mechanical drilling with 0.1mm or less in diameter,with less drill bit breakage and
uniform via side-wall.

To meet future requirements for PWBs,various technologies of processes,materials and tools of PWBs have been discussed.
Especially important are technologies of circuit formation for high-end PWBs. Industrially the circuit formation method for
fine pattern has been changed,in these years,from the subtractive process to the Semi -Additive Process (SAP). SAP can
form finer circuits because it doesn’t cause side etching that is the problem of subtractive method. However the flash etching
process of SAP causes other problems such as short defects due to residual seed metal layer between circuits,circuit etching
and circuit delamination due to etching. Also,because of the roughness of the insulator surface that the circuits are formed
on,there are not only difficulties for fine circuits formation but loss of an electrical property.
In this paper,a new circuit formation method is discussed to overcome the problems that the flash etching process of SAP
causes. It does not need flash etching process therefore it can form finer patterns. The capability of this fine line circuit
formation depends upon the photo pattern resist resolution and was confirmed to perform well at L/S(Line/Space) = 10/10um
or less. Also the circuit pattern is buried in the insulator layer and is planer with the insulator surface,therefore the circuits
have high peel strength with insulator and there is less damage by manufacturing equipment or handling between processes.
This method is applicable to build up PCBs and FCPs as a circuit formation technology that meets future requirements.

Nowadays there are two major ways to achieve the conducting function of HDI Blind Hole One is to employ conducting
metal paste to fill in the blind holes after laser drilling. The other is to fill those mechanical drill holes by means of
conventional PTH technology. Referring to the second way,we discuss how to assess and assure the hole reliability in this
article using several methods of research,we try to demonstrate the relation between the reliability and some requirement
such as blind hole size,copper plating thickness,connecting area of pad in inner layer,under cut,and so on. We hope to
provide sufficient information for the design of blind holes and a set of reasonable design and manufacturing requirements.
When you call your family or friend for an urgent issue using your cell phone outdoors,if your cell phone suddenly does not
work suddenly,no voice,no signal,shut down automatically,and so on,it may cause you to hit the ceiling. This is
particularly true if you try again and the problem is same. Of course,the cell phone maker would rather not leave any bad
impressions in the eye of consumer,especially in the reliability of the phone’s performance.
Why a cell phone does not work suddenly has many reasons. As to the PCB,it may have a circuit connection problem. This is
particularly true in the case of blind holes for HDI that are not easy to find or test. In this article,we discuss the reliability of
blind holes that are formed on the outer layers with HDI technology as well as for those mechanical drilled holes produced by
means of conventional PTH technology. Applying several research techniques based on mass production conditions we will
determine which factors impact reliability and determine what are the reliable design parameter for blind holes that can insure
they can withstand a series of critical test conditions.

As more electronic assemblers move to lead free SMT production,concerns are raised over reflow cooling slopes and effects
on solder joints. Due to the higher peak temperatures,cooling slopes are naturally more aggressive if not controlled properly.
Impacts of variable cooling slopes should be considered for the transition to lead free assembly.
This paper evaluates the effect of variable cooling slopes on lead free solder joints. Controlled testing of lead free assemblies
subjected to various cooling slopes in both air and nitrogen environments is also discussed. Solder joints will be inspected for
solder joint grain structure under differing conditions of aggressive,medium,and mild cooling slopes. Data will be presented on the findings of this study along with suggestions of desirable cooling slopes and reflow system options to best support the
reflow cooling profile.

As lead free assembly is ramping up,wetting of lead free solder pastes is surfacing as the major paste performance tradeoff.
Global efforts to significantly increase lead free wetting chemically have proven unproductive to date. The “drop in” lead free
paste with respect to wetting looks to be improbable. This paper reports the findings of numerous studies using quantitative wetting gauges to measure solder paste wetting to the PCB surfaces. Wetting results with various lead free profiles,reflow
atmosphere oxygen concentrations and lead free PCB surface metallizations are compared and contrasted for their
contribution to maximizing lead free wetting. Although numerous lead free alloys are on the market today,this paper concentrates on the popular SAC (Sn/Ag/Cu) alloy specifically 95.5/4/0.5 in a no clean paste. In addition to wetting,solder
defects and voiding are included in the comparisons to reveal the best overall lead free reflow process.

Traditional reflow profiles for lead-free soldering typically require longer processing times due to elevated peak temperatures
and flux activation times defined by solder paste suppliers. These profiles become particularly challenging when a wide
variety of packaging types are integrated within a single circuit design. Further difficulty is presented when product designs
with high thermal mass,such as heat slugs and metal substrates,are processed. These designs create large thermal gradients
throughout a circuit assembly and add further complexity to finding an “optimal” profile window. All of these issues create a
significant increase in reflow processing times for lead-free soldering.
This paper investigates these increased processing times required for high volume manufacturing of lead-free electronics. A
study of typical process capacity and real throughput capacity is presented. The study evaluates high volume electronics
manufacturing ranging from small circuit assemblies (e.g. cell phone) to large circuit assemblies (e.g. automotive and
computers) and investigates a series of “best” reflow profiles to accelerate the standard lead-free process window to meet a
targeted manufacturing capacity using an automated profiling system. A test vehicle is then fabricated using this defined
process window and tested for quality (solder voiding and appearance) and solder joint reliability (accelerated life testing).
The designed test vehicle includes components from a large physical distribution including: small and large BGAs,QFNs,
and any type discrete components. During assembly,virtual profiling is used to document any deviations to the process
profile window. The quality and reliability data are presented within this publication and failure analysis is included to
determine the capability of this proposed profile.
When employed,this profiling strategy allows many manufacturers to reduce the processing time for reflowing lead-free
circuit assemblies without significant lost in manufacturing quality or reliability. Furthermore,this study provides a sound
understanding and limitations for using accelerated profiling speeds for lead-free soldering applications.