Applications using flip chips in high temperature and high current designs have increased in recent years,and this trend is
expected to continue. Markets utilizing these designs include high performance ASIC,high frequency/RF,and mid I/O
products. The migration of flip chip use into these designs can be attributed in part to the improved solder bump thermal
fatigue life which has been realized with the use of underfills,as well as to smaller final metal pad/passivation openings
being used by IC manufacturers. The need to use flip chips under harsher operating conditions has prompted work to address
reliability concerns with several diffusion related failure mechanisms. These concerns have surfaced in response to results of
high temperature storage (HTS) and high temperature operating life (HTOL) tests. In HTS tests,UBM (Under Bump
Metallurgy) consumption has been observed. In HTOL tests,UBM consumption as well as solder and UBM electromigration
have been observed. On flip chips with a bump structure utilizing eutectic 63Sn37Pb over a sputtered thin film Al-NiV-Cu
UBM,the HTS and HTOL reliability is a function of the UBM thickness – increasing the UBM thickness can have a positive
effect on reliability. However,in general a thin film UBM provides better bump thermal fatigue life,excellent protection to
the underlying aluminum,and is less likely to cause silicon cratering or passivation cracking.
A new approach to increasing the UBM thickness and thereby improving flip chip reliability regarding diffusion related
failures (while maintaining thin film characteristics),is to use an enhanced eutectic SnPbCu solder bump containing a small
amount of Cu in the 1% - 3% range. During bump reflow,the Cu in the enhanced eutectic SnPbCu solder bump has been
shown to precipitate out along the UBM/Solder interface,effectively forming a thicker UBM. This effectively thicker UBM
has been shown to extend the performance life of the structure in HTS and HTOL testing as compared to 63Sn37Pb while
maintaining equal performance in thermal fatigue life as evidenced by thermal cycle (TC) testing. This paper presents data
showing the increased reliability performance of the enhanced eutectic SnPbCu bump structure as compared to 63Sn37Pb.
Assembly and manufacturing characterization data demonstrating the excellent quality and manufacturability of the SnPbCu
bumps is also presented.
The liquidus temperature of SnPbCu alloys increases with increasing Cu %. Increasing Cu % beyond a certain level would
necessitate increased process reflow temperatures. Tests indicate that for purposes of wafer bump and circuit board assembly
reflows,enhanced eutectic SnPbCu alloys in the range of 1% - 3% Cu can be processed using standard eutectic 63Sn37Pb
reflow profiles. Data is presented showing that alloys within this composition range provide significant reliability benefits.

Electroplated pure tin and tin alloys such as Sn99.3Cu0.7%,Sn98%Bi2% and Sn96.5%Ag3.5% have been identified as
viable drop-in replacements to tin-lead solder. High melting point tin alloys such as Pb97%Sn3% and Au80%Sn20% are also
required by the electronics industry for flip chip applications. Capabilities of the commercial pure tin bumping chemistries
will be discussed and demonstrated.
However,commercially feasible plating systems for lead-free tin alloys have yet to be developed. The major difficulty in
plating tin alloys comes from the large difference in standard deposition potential of tin and the alloying metals that result in
poor alloy control and immersion of alloying metals on tin parts and anodes. Enthone Inc. has developed new processes that
allow robust and reliable electroplating of these alloys. We also studied the effect of plating parameters (current density,
agitation,temperature,etc.) and alloy composition on the materials properties of deposited alloys such as voiding,bump
height uniformity across a wafer,reflowability,phase composition,structure,hardness and melting temperature. A few defect
types specific to bump plating and ways to overcome them will be discussed. Recommendation will be made on utilization of
specific finishes for different electronic applications.

There has been much recent interest in printing solder paste onto UBM pads of a wafer. Usually the wafer pad is overprinted
using a stencil aperture that is larger than the wafer pad. This permits optimum bump height after reflow. There is also
interest in printing solder paste onto flip chip pad sites on a substrate such as Fr4 or Ceramic.
This paper will examine stencil aperture designs for bumping applications. The test substrate contains 2 groups of pads;
Group 1 has 4 mil (100-micron) pads on 10 mil (250-micron pitch),Group 2 has 4 mil (100 micron) on 14 mil (350-micron
pitch). Group 1 is divided into 5 sectors of 400 sites per section. The stencil has 5 different aperture sizes for Group 1 ranging
from 5.5 mil (140 micron) to 7.5 mil (190 micron). Group 2 has aperture sizes ranging from 8 mil (200 micron) to 12 mil
(300 micron). AMTX Electroformed Stencils 1.5 mil (38 micron),2.0 mil (50 micron) and 2.5 mil (63 micron) thick are used
to print the Group 1 and Group 2 apertures. Bump height after reflow will be reported for each Group and compared to
theoretical Bump Height and Print Area Ratios.

A conceptual framework for a new type of flip chip attachment is proposed. Gold stud bumps are provided on the chips,and
wells filled with solder paste are provided on a flexible substrate serving as the system board. Pushing the stud bumps into
the wells provides a bump/well connection,and heat is applied to melt the solder and make a permanent connection. An area
array of bump/well connections can have a pitch of 100µ or less. The connections are projected to be mechanically robust,to
support operating frequencies of 10GHz and above,and to support replacement of defective chips as many times as
necessary. Imprinting provides a fabrication method having sufficient precision to shrink the trace and dielectric feature sizes
by a factor of around 20 compared with conventional FR-4 boards,while still maintaining 50O traces. The same precision is
used to eliminate redistribution layers that are normally required between the fine pad pitch of IC chips and the coarser pad
pitch of a conventional board. By also using imprinting to fabricate the wells,a low assembly cost is achievable,potentially
below 0.06 cents per lead. This compares with an industry cost as high as 2.5 cents per lead for performance flip chip
PBGA1. The most advanced materials can be used including copper conductors and Cytop2 as the dielectric. At 10 GHz,
Cytop has a dielectric constant of 2.1 and a dissipation factor of 0.0007. The proposed manufacturing methods and assembly
techniques can be applied to a broad range of microelectronic systems including high performance circuit boards,high
density cables with controlled impedance,integrated passives,and stacked die packages.

Use of solder paste as a material to bump silicon wafers for interconnection to other level of package interconnection is a
simple and cost effective process. However,the material properties of the paste become critical if the quality of the bumps is
to be consistent. Especially critical for high bump quality are low solder balling and low void formation during paste reflow.
Work at Kester Northrop Grumman has shown that flux material properties and powder morphology influence both the
formation of voids and solder balls. This paper will describe a series of experiments that allowed an understanding of these
two major problems. Follow up experiments resulted in a paste that was optimized based on flux composition and powder
morphology.

Manufacturers of consumer electronic products are continuously striving to confer greater functionality to smaller,lighter,
and less expensive packages,and flip chip is an important enabling technology for these product trends. Underfill between
the die and an organic substrate is necessary to compensate for the coefficient of thermal expansion mismatch. The underfill
dispense and cure step is not a typical process for an SMT factory,and demands additional capital equipment,floor space,
cycle time and headcount.
An alternate approach to traditional capillary underfill is wafer applied underfill. The underfill is applied after wafer bumping
and sawing,but prior to the picking of the individual die from the saw tape. This paper describes the coating and assembly
processes. Liquid-to-liquid thermal cycle shock tests (-55oC to +125oC) have been performed on test vehicles assembled with
the wafer applied underfill. First failures were over 1000 cycles. Weibull plots of the data are presented.

The underfill process has become common practice in the assembly of flip chip and CSP devices and the practice of area
array assembly has been adopted by many board designers and component assemblers. The range of devices underfilled has
been greatly expanded and now includes everything from very small silicon devices to stacked die assemblies,MEMS and
display devices. All of these applications have the common problem of smaller amounts of real estate that underfill materials
can be applied to. Additionally,in a number of applications,underfill materials are not allowed to contact die surfaces,
adjacent wirebonds or components.
This increased demand to limit underfill flow onto adjacent components has put pressure on dispensing companies to develop
techniques for putting down small fillets of underfill in a highly controlled manner. A high degree of control of a dispensing
needle tip usually involves slowing the dispensing system down so that a small needle can maneuver into position and
dispense into a tight space. This slows down throughput,therefore a new method of delivering underfill fluids in tight spaces
is required.
This paper will describe the work done to develop a jet capable of dispensing abrasive underfill materials,producing smaller
fillets and high throughput.

During the last several years there has been and continues to be an enormous investment by both governments and industry in
the development and manufacture of fuel cells. The United States,Japan,and European Union have invested billions of
dollars on research and development. Major Universities including MIT,Northwestern,and others have significant fuel cell
research projects. Many large multi-national corporations including all of the major automotive suppliers are investing
billions on fuel cell technology. Fuel Cells are being viewed as an environmentally friendly infinitely renewable fuel source
that will reduce the Unites States and other industrialized nations dependence on foreign oil.
Both large fixed portable fuel cells and portable fuel cells are being developed. Large fixed fuel cells have been available for
some time and are used to power industrial and commercial facilities. Some fixed fuel cells are now powering private homes
in some areas. The goal is to have “thousands” of fuel cell automobiles on the road in the next few years and the majority of
automobiles powered by fuel cells within 10 years. Portable fuel cells are being developed as battery replacements for cell
phones and other common battery powered items.
One of the major issues with fuel cell acceptance is the cost of the energy produced by a fuel cell versus the cost of energy
produced by the competing energy sources. There are several technical challenges to developing cost effective fuel cells.
One of the key areas to reduce fuel cell cost is the manufacturing cost.
Once solutions to the technical challenges are discovered and the cost reduced,high volume fuel cell manufacturing will be a
reality. Can and if so how can high volume electronics manufacturing technology be used to develop and implement high
volume fuel cell manufacturing?
This paper will discuss the use of high volume electronic manufacturing technology,specifically screen printing and mass
curing,in high volume fuel cell manufacturing.

This paper presents a new joining technology for high-temperature application of solder joints,based on the results of the
joint research project "TLSD". By the use of temporary liquid solder joints,it is possible to ensure operating temperatures up
to 200°C or 250°C reliable. After the selection of a suitable base alloy it was possible to develop a stable interface between
liquid solder and solid base metal by special material developments and modifications. In the first step it was necessary to
prove the feasibility,the assembly and testing of functional demonstrators was the main task of the second step. A special
focus of testing was the development of suitable testing methods and strategies to show the reliability of assemblies. First
available results and an outlook for the further development of this new technology will be shown in this paper.

The 3-D interconnection and packaging emerged from the last decade. Today,the 3-D interconnection technologies are
becoming mature and their reliability assessed. 3-D technology constitutes the technical core of the VIGOR project which is
integrated in the European Framework 5 Research & Technology. This European project is called VIGOR for Vertical
InteGration for Opto and Radio (sub)systems. Thanks to the work performed by the consortium members the performance of
the 3-D module will be significantly improved. Applications proposed include the stacking of a wireless module for
automotive,integrating digital levels and a high-frequency level. The applications developed will integrate opto-electronics
functions,i.e. containing optical,opto-electronic as well as electronic parts. To the best of our knowledge,no 3-D module
supplier proposes today these types of applications. As a scientific expertise,thermo-mechanical together with finite element
modelizations and simulations are very crucial. The purpose of this paper is to review with emphasis the different techniques
of 3-D module manufacturing and to focus on the technological developments and the reliability tests performed up to the
mid-term of the project.