Embedding discrete capacitors right into printed circuit boards (PWB),although not new,is part of a pivotal technology for
the PWB industry. For example,the ability to locate decoupling capacitors within a couple hundred microns of
semiconductor I/Os can greatly improve response time and signal integrity. One crucial packaging need,however,is high
capacitance density. High capacitance density can only be readily achieved by ceramic capacitor technology. Therefore,the
focus of this work has been to develop materials and methodologies to embed high capacitance ceramic capacitor layers
inside the layers of the printed wiring board.
Most research in embedding high capacitance ceramic capacitors layers directly into printed wiring boards has focused on
forming capacitors on metal foil at high temperatures. It has generally been assumed that demonstration of good properties of
these “fired-on-foil” capacitors is all that is necessary to be successful. However,in our experience,the greatest challenges to
reliably embedding ceramic capacitor layers inside printed wiring boards reside in the design of the circuit containing
embedded capacitors and the PWB embedding process. Not only does the PWB process have to contend with additional
tolerance issues but,depending upon design,the capacitor may be subjected to aggressive processes and chemicals that may
affect its mechanical or chemical integrity. It is,therefore,incumbent upon the designer to design circuits that can be reliably
made by a PWB shop. This paper discusses these issues and gives some guidelines for design for manufacturing.

The miniaturization of mobile electronic devices continues,market trends toward lighter and thinner printed circuit boards (PWB) have been accelerating. At the same time,the demand for increased functionality of mobile devices has required the
PWB to realize higher density patterning to accommodate more and narrower pitch CSPs on a smaller and thinner PWB. In
order to meet these market demands,IBIDEN has developed a stacked-via structure PWB called “FVSS” (Free Via Stacked-
up Structure). This structure is achieved by filled-via technology,a core technology that fills a laser-drilled hole with copper
plating. The mass production of this technology started in 1st quarter of 2004,and it has proved that,compared to a
conventional type of PWB,design flexibility and total board thickness can be significantly improved. More details regarding the design flexibility,electric characteristics,and reliability will follow.

This article summarises how a copper metallization process for simultaneous via filling and through hole plating was
developed on a laboratory scale and the challenges encountered by scale-up to larger industrial like electrolyte volumes.
Uniform filling and through hole plating on large PWBs was successfully achieved by combining various technologies for
achieving uniform current distribution,hence good via filling efficiency and PTH metallization,independent of sizes and
location on the board surface. Both panel and patterned boards were treated.

This paper describes Advanced Filled Via Plating Methodology for stacked via technology. In this paper,via bottom crevice,
via bottom land etching and electroless copper plating coverage is focused to achieve filled via plating enhancement.

A high-power-SMD-LED (HL-LED) outline 3,3 x 2,9 mm² was developed,with chip-size up to 1 mm² and power dissipation
up to 1.500 mW (400 mA for UV-InGaN) in a corresponding thermal ambient. The thermal resistance is 12 K/W. For high
integrated applications (spotlights,general lighting) special PCBs with isolating layers thinner than 10 µm (commercial solutions:
75 µm) was developed also. Modules on 1 mm copper,area 40 x 40 mm² with 100 HL-LEDs,Ptot = 50 W,Popt = 8 W
in amber (592 nm) and thermal resistant 6 K/W were demonstrated.

In high speed digital interconnects; signal attenuation is a result of both dielectric losses and conductor losses. Previous
works have showed in detail,the characterization and modeling efforts regarding the impact of dielectric loss in PCBs and
the differences between various dielectric materials. Most high speed characterization modeling efforts have not
encompassed the variations in conductor losses due to variations in copper foil roughness or treatments of copper foil for
adhesion. Several recent publications have reported frequency dependent copper losses that do not follow the classical square
root relationship. This paper presents the results for a set of high frequency loss characterizations across various copper foils
and the impact of the copper roughness on the relationship between conductor loss and frequency. Also discussed in this
paper are the implications in high frequency modeling resulting from non-classical conductor losses and the requirements to
ensure causality in simulation results.

Demand for higher speed digital signal processing is notable today in the electronics industry. To meet this demand,circuit
designs that employ coplanar structure,either for both single-end and differential transmission,are increasing. The purpose of
coplanar structure is mostly cross-talk (noise) reduction. It is mostly the case that guard-earth lines are added to microstrip
line or strip line structure to make coplanar structure. However,electro-magnetic field tends to be very complicated for such
structures,and so how the structure is related to characteristic impedance or cross-talk is not well understood yet. For
example,there are some cases where characteristic impedance would be 30% or more different by adding coplanar lines to
simple micro-strip line structure. In these cases,conventional methods will not work well to predict characteristic impedance
with sufficient accuracy. What is making it so difficult is the complicating relation between the signal line references to the
ground layer and to the coplanar lines,and so understanding the electro-magnetic reference mechanism with coplanar
structure is essential to achieve good enough control of characteristic impedance,noise,and cross-talks. We made a detailed
analysis on a coplanar structure and worked out an explanation as to the mechanism with a simple,practical coplanar
structure. In this paper,details of our study on coplanar structures shall be reported,with some proposals as to the design of
coplanar pattern in terms of cross-talk reduction.

Electronic products are being stressed by increasing operating temperatures and higher assembly temperatures. Silicon and
product power consumption are increasing as the silicon densities and signaling frequencies increase. And,the transition to
lead-free solders is resulting in higher thermal excursions during assembly. Both of these conditions are impacting material
selection during product design and are having an impact on product qualification,and influencing long term via reliability.
This paper details the results of an Intel investigation of printed circuit board materials,fabrication processes,and design
variables and the resulting impact on board reliability after lead-free assembly. Results were baselined against standard tinlead
assembly for purposes of comparison. Printed circuit board process and design variables examined included via size,
layer count,board thickness,and laminate material. Also examined were the variation within an individual supplier and the
variation across multiple suppliers using the same materials. The paper details the test board configurations used in the study,
the lead-free and tin-lead assembly profiles to which the boards were subjected,and the test methods employed to collect the
data. The test data highlights key trends in the reliability data as a function of changes in the variables tested.

Lead products are no longer an option if you want to export to the EU market. RoHS regulations requiring the manufacture of
lead-free electronic products by July 2006 are pushing the industry to evaluate and find lead free solutions soon. There are
several important issues in undertaking a transition to lead free,including: 1) finding PCB materials and plating finishes that
can withstand the high reflow and wave temperatures of lead free alloys,2) selecting lead free alloys that have similar or
better quality and reliability characteristics than SnPb,3) assessing whether the lead-free components can withstand high
reflow temperatures,4) finding a cost effective solution,and 5) understanding and solving the challenges of the lead-free
process on PCBs,components and solder joint quality. In this paper we address these issues by evaluating a) two PCB
materia ls - FR1 and FR4,b) PCB plating finish – OSP and Ni/Au,c) lead-free alloy Sn 3.5Ag0.5Cu (SAC) and 58Bi42Sn,
and d) the number of reflows (single -sided vs. double-sided). We evaluated 58Bi42Sn eutectic alloy as a solution for those
components that cannot withstand the high temperature process of SAC alloy. Our goal is to determine a cost effective
solution for a low temperature application. Different reliability tests,warpage measurements,and cross sections were used to
evaluate each configuration.

Environmental regulations are forcing the elimination of lead (Pb) from electronic equipment. 2005 will be the year that
many electronics assemblers will be transitioning their soldering processes from traditional tin-lead alloys to lead-free alloys.
Many alternatives to tin-lead have been proven to be technically viable in relatively small volumes,but the implementation of
the new processes in high-volume manufacturing presents a series of new challenges to engineering and operations personnel.
This paper reviews six major considerations for implementing lead-free soldering processes in a manufacturing operation:
equipment evaluation,materials compatibility,separating and identifying the two separate processes,training,validating the
process,and beginning continual improvement. Details of each consideration are discussed and summarized in a checklist
format at the end of the paper.