The comparison of the thermal pattern and the deformation pattern both are obtained on the surface of Printed Circuit Board
(PCB) was done to understand how both patterns correspond to each other. In the present study,both the FEMLAB simulator
and Thermography were employed for the study.
A Holographic Pattern Measuring System (HPMS) and an Interferometry Imaging System (IMS) were used. The test results
showed that both thermal pattern and deformation pattern were different from each other. We found that we could not deduce
the thermal deformed pattern on a PCB from its thermal pattern.

This paper describes part of a research effort currently under way in the field of print defect detection. The techniques
described have proven to be robust and particularly well suited for detecting troublesome bridge and bridge-like features that
span the gap between pads.

After the world electronic circuit industry finally turned out from the unprecedented recession,the business management of
today’s printed circuit industry may possibly have a chance to take a comfortable breather for a while. However,looking into
the trends and drivers of the industry,many people are still endeavoring to look for the next step in business development as
the competition environment is changing so rapidly. Today,China’s electronics market catches much attention for the
business people both in China and around the world. Driven by relocation,restructuring and supply chain management and
changes in China’s electronics manufacturing market and printed circuit supply,there are more features of China printed
circuit industry today,both with market opportunities as the industry is developing and with challenges which have to be
watched and turned into business development opportunities. Behind the growth of the China printed circuit market,there is
much more to improve and to collaborate.

The world market is changing for the OEM,CEM,and electronic manufacturers. This changing market dictates that as a
global industry more focus is placed on reducing the time to market for “New Product Introduction”. The current process has
many redundant steps and requirements that greatly vary from one OEM or CEM to another. The transfer of the data and
information required to build the design are ineffective. Often the fabricators receive designs with erroneous or incomplete
information,resulting in even more delays in introducing the product to the marketplace. This is further compounded because
prototype PCBs are frequently built at one facility and then transferred to another manufacturer or split between manufactures
for production. The problems that are found at the prototype stage are not fixed before it is transferred to production,and the
new production facility must once again deal with the same issues as the prototype manufacturer.
As the intricacy of the NPI process and the complexity of design requirements increase,the need for software tools grows
dramatically. A fully integrated process from predesign analysis,where the designer is determining the initial characteristics
of the design,through to the final product reaching the customer is essential,given today’s environment. This paper describes
a process that builds value into each step of the NPI job flow and retains the information for use throughout the entire
process. Quality checks must be performed throughout the NPI process,and the design integrity must always be maintained
even when transferring the design from one manufacturer to another. With the global placement of designs for prototyping
and production,consistency in the design’s performance,regardless of where it is manufactured,and a historical record of the
design’s life cycle are necessary so that the product’s performance is never compromised or derogated.

It is effective to use the stack-via-holes method (via-on-via structure),which stacks micro via-holes (MVH),in the
development of higher density circuits on build-up printed wiring boards. When micro via-holes are repeatedly stacked,via
holes cause an open circuit due to the difference in the thermal expansion of the copper and the glass epoxy base material. In
order to verify the reliability of the stack-via-hole connection,we produced a range of test boards with differing numbers of
stack-via-hole layers,material types (FR-4,high-Tg FR-4,low thermal expansion material,etc.),and via hole diameters
(0.100 mm and 0.075 mm diameters). The boards were examined through DC current induced thermal cycling tests to
determine the reliability of the various samples.
In respect to the anti-migration properties,we also undertook research on pitches and base material types of micro via- holes.
As a result of the evaluation,it was verified that the MVH,then interstitial-via-hole (IVH),followed by the plated throughhole
(PTH) achieved the best connection reliability. As for base materials,it is recommended to use a high-Tg material with
low thermal expansion qualities. We believe that an MVH diameter of 0.100 mm is preferable to prevent any void attributed
from a high aspect ratio. No problem with the insulation reliability was found on any base material as long as the MVH pitch
is 0.35 mm or more (or 0.25 mm between the hole walls).

We report test results of bending characteristics of flexible printed circuit board,which contributes to the development of
higher density and more sophisticated function of mobile devices and electronic equipment. Our report shows that there is a
correlation between mechanical structure and the bending characteristics of flexible printed circuit boards,and that ultra thin
structure shows excellent performance in bending applications. We also find that elasticity modulus of adhesive plays a key
role in the bending characteristic of flexible printed circuit board. We have utilized the finite element method to evaluate the
strain for investigation of the bending fatigue mechanism. We will report on the study of a formula with which we can
estimate the flexural fatigue life. We also show the analysis result of generated stress when various constructions of flexible
printed circuit boards are bent.

It has been reported by several laboratories that the time to delamination or decomposition of a printed circuit board specimen
at 260°C decreases with the specimen thickness. A temperature gradient across the thickness of the sample within the furnace
of the Thermomechanical Analyzer (TMA) was the suspected cause. Testing laminate specimens with embedded
thermocouples,the temperature gradients within two major brands of TMAs and at several laboratories was determined to be
approximately 2.5 to 3°C per millimeter. This temperature gradient results in a 20°C difference between the top and bottom
of a 7 mm thick specimen. Modifications of the T260 test parameters,such as thermocouple location during the test and
thermocouple calibration procedure are recommended.

A series of electrical plating processes to build various kinds of micro bump arrays on the organic substrates has been developed for non-permanent connections. Copper bump arrays with nickel/hard gold plating on the organic substrate with small pitches have been required for the non-
permanent terminations. Electrical test probes of the semiconductors and micro size components have been demanding reliable micro bumps on the organic substrates for the repeated contacts of more than one million times. Several combinations of the micro hole generation processes and the electrical plating processes have been developed to
satisfy the requirements. The new electrical plating processes are capable of building the micro bump arrays with copper,
nickel and hard gold for pitches smaller than 50 microns on the substrates of FR-4 boards and polyimide films with epoxy or polyimide insulation layers. The plating processes provide broad choices for the shapes and heights of the micro bumps with copper,nickel and gold. Several drilling processes have been introduced to generate small holes with high dimensional accuracy for the exact alignment of the micro bumps on the narrow traces. A series of studies were conducted to review the capability of the drilling process. The whole process has a broad capability for the all kind of organic substrates. A set of design guidelines has been introduced to optimize the productivity.

With the progress of miniaturizing electronic equipment with higher performance,packaging substrates for semiconductor
devices are required to cope with finer patterning and higher wiring density. The semi-additive wiring process has been
needed in place of the conventional subtractive wiring process because the former can achieve higher wiring density than the
latter. To realize high-density wiring,the surface profile is very important. Besides wiring process ability,improvement in
several properties has been required because high-performance and complicated packaging substrates need higher reliability
and lower transmission loss.
A new insulation material for the semi-additive process has been developed in these situations. This new material is
applicable to the semi-additive process and features higher elongation,better dielectric properties,satisfactory plating peel
strength with smoother surface profile,as well as being environmentally friendly.
In generally,most of the thermosetting resins,including epoxy resin,have a fragile nature compare to the thermoplastic resins.
However,this new materials has relatively low modulus and high elongation in spite of using epoxy resin-based material; it
also has a low coefficient of thermal expansion (CTE). The material proved to have enough insulation resistance and
electrical reliability. The transmission loss for the material was smaller because of its lower surface profile. This new material
is expected to find applications as an insulation material for next generation packaging substrates.

We have developed the copper high density wiring formation technology with Cu/photosensitive Benzocyclobutene (BCB) as
a dielectric material,and interconnect technology with Silicon through-hole. The basis is four-layer structures with copper
conductors and BCB dielectric formed on the core substrate. We have adopted stacked via structure as multi-layer and the Si
wafer for core substrate. We selected the metal titanium as an adhesion layer between the conductors and the dielectrics
before copper conductor layer formation. We measured the adhesion strength between conductor metal and BCB using the
90-degree peeling test. The peeling strength becomes stronger than 0.50 kN/m by performing the suitable pretreatment on the
BCB. The core substrate is composed of copper plugs,which connect the front and backside of the wafer electrically. The
copper plugs are 30 µm in diameter and 250 µm depth. We have succeeded in production of plugs without voids and have
confirmed good reliability by THB test and the heat cycle test.
We have also measured and simulated the fundamental transmission properties of micro strip line of Cu/BCB multi-layer
wiring structure and compared with the another dielectric material such as PI and Fluorene. The frequency was swept from
100 MHz to 40 GHz,and two-port parameters such as S11 (reflection) and S21 (transmission) were extracted. The result is that
transmission loss of BCB is maintained about 1.5 dB at 30 GHz,when the line length is 5 mm and the line width and space
are 10 µm /10 µm. It was most excellent in especially high frequency range as compared with other dielectric materials. We
obtained approximately same result also in the simulation. We have confirmed good agreement of transmission properties of
micro strip line structure between simulation and measurement data.