The commercial use of lead-free solder has been making significant gains worldwide in recent years. To identify the effects
of thermo-mechanical stress on Sn-Ag-Cu and Sn-Zn-Bi solder with different lead finishes (Sn-10Pb,Ni/Pd/Au plating),we
performed the following reliability tests: high temperature tests,thermal cycle tests,and combined thermal-vibration tests.
Following the tests,we investigated the causes of degradation by checking solder joint strength and observing solder joint
cross-sections.
Our investigations indicate that the same level of reliability can be obtained with Sn-Ag-Cu solder as with conventional Sn-
Pb eutectic solder. On the other hand,in response to thermo-mechanical stress,Sn-Zn-Bi solder forms voids and intermetallic
compounds at the joint interface between the solder and the printed circuit board (PCB),resulting in a loss of joint strength.
We then used Sn-Ag-Cu solder in mass production prototype PCBs. We subjected these PCBs to a variety of reliability tests
and carried out three years of field reliability testing. These PCBs with Sn-Ag-Cu solder held up successfully under a
minimum of 3,000 cycles in thermal cycle tests and a minimum of 20,000 hours in field reliability testing.

Developing lead free connector products involves at least two distinct steps: removing the lead from the product and ensuring
the product has sufficient thermal stability. Lead is most commonly found in terminal finishes and has been removed from
most thermoplastic materials used in connectors. Ensuring sufficient thermal stability requires knowledge of the thermal
excursions involved in soldering and how these excursions translate into product performance metrics.
For reflow soldering,we know the maximum soldering temperatures will increase by 20 to 30 °C. The magnitude of this
change is not large,however,the temperature value,260 °C,exceeds the melt point of many engineering thermoplastics.
Since the cost of these plastics typically scales with melt temperature,an increase in thermal requirements can mean a
significant cost increase.
In this paper we strive to understand the fundamental response of the plastics to the transient thermal excursions involved in
wave soldering. FEM simulations demonstrate the thermal gradients that exist during these processes. These results can be
used to understand the heat transfer and then to engineer the products to ensure reliability. Wave solder process simulation
shows that the pin to plastic interface resides at a temperature very near to that of the solder. Connector terminals,made from
copper based alloys,often have very high thermal diffusivities,increasing heat flow from the solder pot into the plastic. FEM
results are compared to experimental results from lab and production manufactured testing of solderable interconnects. A test
method for evaluating plastic performance in wave solder applications is proposed.

An issue that has emerged from the increasing use by the electronics industry of lead-free solders in mass production wave
soldering is the erosion of the copper of printed circuit board patterns and component terminations and the stainless steel of
the wave solder bath. In the study reported here the wetting and erosion of copper and Type 304 stainless steel by two widelyused
lead-free solders,Sn-3.0Ag-0.5Cu and Ni-stabilized Sn-0.7Cu,was compared with that of Sn-37Pb and Sn-0.7Cu with
and without the addition of phosphorus antioxidant. The rate of dissolution of copper by the Ni-stabilized Sn-Cu alloy was
found to be lower than that of pure Sn-37Pb alloy while that of the Sn-3.0Ag-0.5Cu and Sn-0.7Cu alloys was higher. The
addition of phosphorus increased the copper erosion rate of both lead-free alloys well beyond that of Sn-Pb. The rate of
erosion of stainless steel by lead-free solder was confirmed as faster than that of Sn-Pb eutectic solder and phosphorus was
found to promote the wetting that precedes erosion. The rate of erosion of stainless steel by the Sn-0.7Cu solder was
significantly slowed by the addition of nickel.

Major industrial nations,around the world,are rapidly moving to eliminate lead from the electronic manufacturing processes.
While some companies are taking advantage of the situation and are using “lead-free” as a major marketing initiative in the
consumer market,others are delaying the inevitable,because of the world wide lead-free legislation.
Lead-Free Legislation
Europe
• OECD: Lower the lead content limit in underground water from 0.05mg/L to 0.025mg/L in 2000.
• Total abolition of lead,cadmium,hexa-chromium,and non-flammable agent halogen starting 2005/6,according to the
EU directive (WEEE & Rosh).
USA
• 1990: Introduced a bill prohibiting use of solder containing over 0.1% lead. (However,this excludes the electronics
industry.)
• 1999: Industrial organization NEMI,formed by the USA electronic parts manufacturing industry,government
organizations and universities,started research and development targeting the total abolition of lead products by 2004.
• 2002: Proposition 65 California.
• End Of Life legislation pending in 20 plus states.
Japan
• 1991: The Waste Disposal Law requires disposal within the facility when the detected lead amount is over 0.3mg/L by
eluting test of industrial waste.
• 1994: The Water Pollution Prevention Law lowers the lead content of rivers from 0.1mg/L to 0.01mg/L.
• 2001-4: The Consumer Electronics Recycle Law requires manufacturers to recover harmful materials.
The move to lead-free solder has an impact on all phases of PCB assembly,including test and inspection. Let’s take a look at
some of the technical issues involved and the impact of lead-free solder on the major test and inspection technologies:
automated optical inspection (AOI),automated X-ray inspection (AXI),in-circuit test (ICT) and functional test.

The hypothesis that the “whisker growth phenomenon” in electrodeposited tin is a re-crystallization process driven by stress
has gained popularity among leading research institutes and industrial laboratories. However,there exist varying opinions as
to the type of stress responsible for this phenomenon. Recently,various studies have demonstrated that compressive stress,
whether intrinsic or externally applied,is most likely the cause of whisker growth.
There are three main sources of compressive stress that a component finish experiences after plating. They are: stress
generated by intermetallic compound formation between the tin finish and the copper alloy substrate; mechanical stress such
as trim-and-form introduced in current manufacturing practice; and thermal stress generated by temperature cycling and
propagated into tin layer due to CTE mismatch among the constituent materials of a component.
It is well recognized that both IMC formation and CTE mismatch are largely affected by the substrate material and
underlayer/barrier between Sn and substrates,as well as aging conditions. In this paper,we attempted to understand the
relative contribution of stress generated from IMC and from CTE mismatch on various leadframe and connector substrates at
both isothermal and temperature cycling conditions. Ultimately,we hope to delineate the whisker accelerating factors to
provide input for the industry to derive a set of standard yet realistic whisker test methods.

Tombstoning of SnAgCu is affected by the solder composition. At vapor phase soldering,both wetting force and wetting
time at a temperature well above the melting point have no correlation with the tombstoning behavior. Since tombstoning is
caused by unbalanced wetting force,the results suggest that the tombstoning maybe dictated by the wetting at the onset of
paste melting stage. A maximal tombstoning rate is observed at 95.5Sn3.5Ag1Cu. The tombstoning rate decreases with
increasing deviation in Ag content from this composition. DSC study indicates that this is mainly due to the increasing
presence of pasty phase in the solders,which is expected to result in a slower wetting speed at the onset of solder paste
melting stage. Surface tension plays a minor role,with lower surface tension correlates with a higher tombstoning rate.
SnAgCu composition with a Ag content lower than 3.5%,such as 2.5Ag,is more favorable in terms of reducing tombstoning
rate with minimal risk of forming Ag3Sn intermetallic platelet.

Whilst the number of new ASIC designs has decreased over the last couple of years,there has been a dramatic increase in the
number of FPGA designs implemented. Not only have the number of designs increased rapidly,the complexity and also the
size of these devices have grown over this period. In the early 1980s,the first PLD devices had around 300 gates,while
today’s FPGAs exceed two million gates. Along with the increasing FPGA gate count there has been a corresponding
increase in the number of available I/O pins such that there are over 2000 pins available on the largest BGA packaged FPGA
today. As FPGAs continue to grow larger and more complex,it seems that the design tools used by the design engineers
become increasingly unsophisticated. Which begs the question: How are designers going to place these large components on
to a PCB in an automated and consistent way?
Since the problem spans the two processes of FPGA and PCB design,it is difficult to decide where a solution should be
created. Central to this discussion are the problems of symbol creation and I/O assignment,and given the fact that it concerns
the two processes,how to keep the information consistent between them. This paper discusses the problems and possible
solutions to integrate today’s large FPGAs on a PCB,where subjects like scalability to larger/smaller devices,corporate
library structures and the origin of the I/O constraints will be discussed. This paper also addresses some ways to help
overcome these FPGA integration problems by using the right tools.

As digital data rates reach 5Gb/s,10Gb/s and beyond,digital designers are finding it increasingly difficult to meet their
design constraints using FR4. While there are a host of alternative materials available,cost constraints often prohibit the use
of these materials as their increased performance brings a proportional increase in price. An often overlooked compromise
solution is available which gives substantial improvements to the loss characteristics of high speed layers by using a mixed
stripline construction which pairs FR4 with a high performance material such as those available from Nelco,Rogers,and
W.L. Gore. This paper addresses the question of the potential benefits of mixed dielectric stripline construction by comparing
the crosstalk and insertion loss performance of hybrid (mixed dielectric) stripline constructions to industry standard,
homogeneous PCB stackups. Data is obtained both via direct measurement of test traces and via simulated results. Finished
PCB cost-performance considerations are also presented for the constructions evaluated in this study.

The electrical properties of PCB substrates are one of the primary factors used in designing high-frequency printed circuit
boards. The loss tangent is the electrical property used by material suppliers to characterize the signal integrity of the PCB
substrate. OEMs will perform additional electrical tests to characterize the performance of a PCB substrate before deciding to
approve it for use in a design. This paper will discuss one technique used to characterize signal integrity by an OEM.
Additionally,this test will be compared to values provided by material suppliers to determine the degree of correlation.

The need for dynamic compact models for Integrated Circuits (ICs) is a well-recognized problem in electronics cooling
simulations of electronic systems. Simplified thermal models have been reported in literature to simulate steady-state and
transient thermal behavior of IC devices. Most of the simplification approaches require a pre-determined topology of a
resistance-capacitance (RC) network. Multigrid technique allows for automatically constructing both the topology and
characteristics of the reduced-order or compact models of devices (primarily IC packages) for use in system-level
simulations. In this study,we report an approach where the topology of RC networks is automatically generated. The
topology of the RC network is not predetermined and can be automatically changed to meet the modeling accuracy
requirement. The procedure is robust for packages with various degrees of complexity in both automatic construction of RC
network topology and automatic extraction of nodal RC values. The procedure is also applicable for complex IC sub-systems
or systems like multi-chip modules,stacked die package,system-in-package,and CPU module,and hard drives.
In the study report herein,the method is applied to a 196-pin fine pitch ball grid array (FBGA15x15_196L) package. An RC
network is created for the package and then used in a transient CFD simulation under single phase natural convective cooling
in JEDEC chamber. The simulation results using the RC network model are compared to the corresponding detailed package
simulation.