When using standard approaches to PCB design and manufacture,there are a number of different elements that can impact
signal integrity at high data rates including: inconsistencies in dielectric properties,inconsistencies in trace width,variation in
circuit spacing,uneven copper thickness and/or adhesion treatments. All these attributes reduce the signal integrity engineer's
ability to predict and design for maximum performance. When tied to the range of electrical concerns such as resistance,
dielectric loss,conductor loss,stray capacitance elements,signal skew and inductance which can lead to cross talk and
potential reflections due to electronic stubs from circuit features such as vias,one quickly sees a compounding of the
problem. It becomes evident that new approaches to solving these problems are required. While improvements in materials
and manufacturing processes have yielded some improvements,signal integrity experts still warn of the future impact of the
limiting elements of current approaches to printed circuit design and manufacture. Thus it becomes clear that a new and
better way of addressing these problems is to simply avoid the traditional design approach path in favor of new design
methods that break the manufacturing challenge into more manageable pieces.
This paper will examine and describe such methods incorporating fundamental approaches,which three-dimensionally
partitions printed circuit design and in the process segregates high speed signals from lower speed signals and power and
ground connections. Novel methods and structures that accomplish this objective illustrate how high speed signals are
interconnected by means of controlled impedance links that are fabricated separately from the PCB and later interconnected
directly between IC packages where required. Thus instead of trying to precisely control a complex printed circuit design into
a monolithic interconnect the signals are instead segregated and critical signals are shepherded to a more easily controlled
interconnection paths that lead directly from chip-to-chip or chip to other suitable electronic device.

The IPC study mentioned in the title looked at the effects of time,temperature and humidity on the solderability of true bare copper,immersion silver,immersion tin,organic soldering preservative,reflowed tin/lead and immersion gold/electroless nickel circuit board finishes. In the study solderability was measured by the traditional,qualitative dip and look test; by wetting balance and by SERA. This present examination centers on the results of the wetting balance and SERA work. Data for time to zero,time to two thirds maximum wetting force,maximum wetting force and the SERA parameters V2 and Vf were all examined in an attempt to see which are related. Some correlations were found that may be useful.

The deployment of non-Lead (Pb) surface finishes is well underway throughout the electronics industry. Printed circuit boards,which for many years had relied on Hot Air Solder Level (HASL) finishing,have been using new flatter,Pb-free solderable finishes. Market tracking surveys indicate that the use of HASL has dropped below 50% of all PCB’s. HASL alternative finishes include Organic Solderability Preservative (OSP,) Electroless Nickel Immersion Gold (ENIG,) Immersion Silver,and Immersion Tin. While there are significant differences among the HASL alternative coatings,they do have certain characteristics in common. All HASL alternatives are much flatter and thinner coatings than HASL.
PCB surface finishes need to perform several functions. Archived literature provides information on the solderability,contact functionality,solderjoint reliability,and high speed signal integrity effects of the surface finish options. The summary contained herein describes a fundamental criterion of all board finishes: the ability to protect copper for subsequent soldering and field use. The surface finish,and therefore the underlying copper,can be compromised by exposure to harsh environments such as air pollution,condensing moisture,ionic liquid solutions,and contact with corroding materials. Surface finishes are more or less degraded based on the sensitivity of the surface finish to environmental contaminants and the thickness of the protective coating. For example,tin/lead is not especially resistant to corrosion,but it does have the advantage that it is deposited to such a thickness that it withstands corrosion relatively well.
Corrosion of copper circuitry begins as thin tarnish of the surface finish. Circuit functionality will be compromised only if the chemical pollutants,and the means to convey the pollutant,are present long enough to corrode the copper. This paper reviews some specific causes of corrosion,methods used to measure the corrosion,functional aspects of tarnish and corrosion,and methods employed to prevent surface corrosion. Of special interest,this paper reviews the use of ultrathin layer of tarnish protection on new HASL alternatives such as immersion silver. More specifically,the topic of creeping corrosion will be discussed as an example of the extreme results of tarnish and copper migration.

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While silicon density doubles approximately every 18 months,following Moore’s law,PWB electrical technology advances much more slowly,Up until now trace impedance has been a sufficient high speed electrical specification for PWB traces. PWB manufacturers utilize time domain reflectometry (TDR) to measure trace impedance. The original IPC specification for TDR was written 20 years ago by this author.
Emitter Coupled Logic (ECL) logic drove need for controlled impedance early in the seventies,and considerations of topology and reflections have for some time been the main task for signal integrity engineering. Inevitably,the speed march has pushed gigahertz signaling onto the PWB,which presents new design challenges. At GHz frequencies,for instance,trace loss is actually more important than impedance. New materials and processes for RoHS could affect board loss characteristics.
Traditional loss measurements are done using vector network analyzers (VNA) which are costly and not well suited for a PWB manufacturing operation. A new IPC committee,D24a,has been tasked to develop a low cost TDR/TDT loss measurement method that can utilize pre-existing PWB equipment. The committee’s objectives are to develop a low-cost but accurate loss measurement method which empowers PWB manufactures to manage development of low-loss materials and manufacturing methods.
This paper will detail how a single TDR/TDT pulse energy value can be used as a loss specification. It will be shown how this single value method is as serviceable as a VNA measurement,while doing away with the exacting procedures required for the VNA approach.

This paper presents the qualification of a new,very thin,printed circuit board (“PCB”) dielectric substrate (“core”) to meet Teradyne’s performance and reliability design goals for a power supply (“PS”) printed circuit board.
The challenges included lower noise margin and higher current carrying capacity. These requirements needed to be met while reducing total product cost and improving system reliability. Newly available copper clad polyimide cores,if they were reliable,could provide a solution to achieving the design goals.
This paper provides details on: A) the design requirements and achievements; B) the core used,a copper-clad 25 micron [0.001"] polyimide film; C) an overview of the performance and reliability testing and results; and D) a quick look ahead at next generation even thinner cores for low inductance and electromagnetic interference (“EMI”) reduction.

Lead-free soldering is expected to become the new standard in the future. Different legislations or draft directives target the restriction or the ban of the use of lead in the world. As an example,the European Union adopted the Restriction of Hazardous Substances (RoHS) Directive in January 2003. It will come into effect on July 1,2006. Most of the lead-free solder alloys melt at higher temperatures than that of the eutectic SnPb solder. The change to higher temperature solder alloys will directly affect the temperature profiles for reflow soldering,wave soldering,rework and repair. Typical lead-free reflow profiles will reach peak temperature of 245°C to 265°C for up to a minute. De-soldering,rework and repair will reach peak temperature above 300°C for a few seconds. In parallel,the complexity of the boards is increasing,leading to thicker multilayer structures. Laminates will thus be submitted to higher temperature for longer time through multiple reflow cycles. It is critical to understand how these new technical requirements will have an impact on the thermal resistance of electrical laminates.
This paper aims to provide correlations between different techniques used to characterize the thermal stability of electrical laminates suitable for lead-free soldering.
• Thermo-Gravimetry Analysis (TGA) was used to measure the degradation temperature (Td) and the time to degradation at a given temperature (D-260,D-288,D-300);
• Thermo-Mechanical Analysis (TMA) was used to measure the time to delamination at a given temperature (T-260,T-288,T-300),the number of temperature cycles before delamination (Nd),and the coefficient of thermal expansion along the z-axis (CTE);
• Differential Scanning Calorimetry (DSC) was used to measure the glass transition temperature (Tg).
The thermal stability data of various epoxy systems will be described and correlated to specific applications needs. Various examples of epoxy systems will be chosen within the portfolio of The Dow Chemical Company.
Results suggest that conventional FR-4 resins might still be suitable for standard FR-4 applications that need only a few lead-free reflow cycles. When the number of cycles increases,enhanced resin systems must be considered to avoid in-process failure. Highly thermo-resistant products are suitable for complex multilayer build-up or for applications targeting high in-use temperature. In addition to thermal stability,other key laminate parameters for board reliability are adhesion and toughness.

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Embedded passive components are resistors,capacitors and inductors buried within a multilayer PCB. Embedded components pass standard reliability test methods,however,the higher temperatures required for lead-free solders increase the physical stress in the board. Component failures,although rare,are typically caused by high z-axis expansion,
lifted pads or innerlayer delamination that cracks and/or opens the embedded component.
High performance laminates designed for lead-free assembly offer a higher Tg and decomposition temperature and a lower CTE but bond strengths are lower than a corresponding FR-4 substrate. Metallic embedded components can withstand higher temperatures than organic substrates,however when the PCB is tested to failure by multiple solder shocks,the embedded component layer fails preferentially due to the lower bond strength.
A Design of Experiments for a PCB with embedded passives and lead-free assembled SMTs showed that laminates with light weight glass and high resin content giving the best results (no delamination after multiple thermal excursions). The conclusion is that embedded passives in multilayer PCBs built with high performance laminates using improved copper topographies,high resin content and light weight glass constructions are reliable for lead-free assembly.

Over the past six years Motorola has shipped over 47 million phones incorporating Embedded Passives (EP) technology. The EP modules shipped in phones have included small modules such as voltage controlled oscillators as well as large modules comprising full phone functionality. Driving the creation of a supply chain—from materials supplier through board fabricator—was also required in order to execute the transformation of embedded passives from R&D curiosity to reality in products. Every implementation of EP has maintained system cost parity or reduced system cost while benefiting from size and routing complexity reduction. This paper briefly reviews the commercialized portfolio of embedded resistor,capacitor,and inductor technologies,and uses several case studies to highlight the lessons learned.