Selective electrodeposition (brush plating) was successfully used to rework a solder-contaminated, hard gold-plated copper flag connector for a circuit card assembly (CCA). The localized repair methodology of brush plating eliminated the need to scrap a number of CCAs that otherwise could not be reworked with conventional bath plating processes. The flag contacts on the CCA were chemically stripped to remove the contaminated gold to expose the nickel-plated copper substrate. Hard gold (Au) was applied to meet the drawing requirements. To characterize and understand the quality of the rework process, plating repair and rework were prepared on separate flag connectors, which were applied via a pencil application process and a brush plating process. Surface morphology and environmental resistance were evaluated to understand the differences among the brush plating, pencil process, and bath plated control specimens. The reworked flag connectors were also evaluated for wear resistance in comparison to conventional bath plated connectors. Results implied that the hard gold brush plating rework was dense, smooth, and uniform, with comparable wear characteristics to the bath plated control sample. The conventional hard gold bath plating flag connectors contained process artifacts that were exposed with environmental testing that were consistent with the features of the brush plating flag connectors. The lack of uniformity and presence of process artifacts in the manual pencil repair contributed to poor environmental resistance. Overall, environmental resistance and wear behavior of the brush plating flag connectors were similar to the control specimens prepared with conventional bath plating. Edge effects did not contribute to adhesion defects or blisters in the brush plated connectors.

The iNEMI flowers of sulfur (FoS) corrosion chamber was developed to study creep corrosion on printed circuit board assemblies(PCBAs). The chamber, typically run at 50 or 60oC, has corrosive sulfur and chlorine gases along with relative humidity controlled in the 11 to 90% range. The sulfur gas is emitted from a bed of sulfur and the chlorine gas from household bleach containing 8.25% sodium hypochlorite. The chamber has been used to study creep corrosion. It has reproduced creep corrosion on PCBAs from manufacturing lots that suffered creep corrosion in the field; shown that creep corrosion is a function of relative humidity; shown that creep corrosion originates where the solder mask overlaps the copper metallization on printed circuit boards (PCBs); and shown that PCB storage time reduces creep corrosion propensity in service. In addition, preliminary investigations have shown the chamber to be useful in determining corrosion rates of copper and silver as a function of relative humidity and temperature and for conformal coating characterization. The paper will review the above examples of the successful use of the iNEMI FoS chamber in addition to the research currently underway to develop a qualification test for surface mount resistors at a more realistic temperature of 70oC. The current qualification test for these resistors is run at an unrealistically high temperature of 105oC which most probably causes the resistors to fail with a mechanism different from that in the field.

Environmental dust accumulation on electronic equipment can impact the performance and reliability of the equipment in various ways. This includes mechanical effects (such as obstructions of cooling air, moving parts and optical interference), chemical effects (such as corrosion and metallic dendrite growth) and electrical effects (such as impedance reduction, short and open circuits). Minimization of dust deposition on electronic equipment is necessary and beneficial to product performance and long-term reliability. This work focuses on one aspect of reducing dust accumulation on electronic equipment, specifically by optimizing the cooling air flow.

Inspection means have increasingly been incorporated into typical manufacturing of boards, substrates and/or systems. A significant number of automatic inspections rely on the analysis of images that are acquired by a multitude of means such as Optical, X-Ray, Infrared, Acoustic microscopy. In contrast to automatic inspections, traditional visual inspection is performed manually by humans based on images and can be laborious and inaccurate. Detection of “indeterministic” defect types such as cracks and/or scratches is quite challenging since such defects may have a variety of shapes, locations and severity. Deep Learning, a subfield of Machine Learning, has recently advanced the state-of-the-art learning from images and become the standard approach for computer vision tasks. This paper presents a case study for automating visual inspection of boards by as much as 40%. The application can be extended to identify specific types of defects and to support root cause analysis.

Digitalization changes everything, everywhere. It is inevitable, new business drivers are forcing the Electronics industry to rethink every element of their business. Virtually every company is talking about innovation and digitalization. And a major driver is the so-called Digital Twin. While talking about this Industry 4.0 enabler, most people have one benefit in mind: Aggregating the data in a cloud and integration of artificial intelligence for future enhancements which lead to an optimization of the operation. Another one is the simulation of a product and derive the behavior in certain conditions. Both are covering only one certain aspect of the product lifecycle from product design to production execution while there is so much more possible by utilizing the concept of the digital twin in the production engineering phase via Virtual

Commissioning. Streamline the activities of all disciplines involved in the physical commissioning of their automated production systems, reducing errors and increasing the speed in which they bring automated manufacturing systems online by writing the controller program and building the machine at the same time. The paper will review the different digital twin concepts in production:

-Digital Twin of the product: Product design, Hot Spot simulations and adoptions, simulate PCB circuit design-Digital Twin of production workflow: Machinery design, production layout, simulation of production steps & continuous improvement including manual labor-Digital Twin of manufacturing: The emphasis of the presentation will be within this discipline of the digital twin. Steps

1.Write PLC (Programmable Logic Control)/Controller code for machine operation

2.Define sensor and actuators (conveyors, robots, grippers,...) in the CAD model as input and output signals according to the PLC code

3.Define collision models and kinematics in the CAD model (e.g. a product falls over at the end of a conveyor belt or a robot arm must not collide with the chassis of the production cell)

4.Test your machine functionality in the digital twin.

Since physical behavioral model is defined within the CAD model the integration of the PLC code allows to detect failures in the construction of the machine (e.g. robot arm cannot reach a defined position in the process or conveyor belt cannot transport defined parts smoothly) which can be corrected prior to the actual construction of the machine. As a result, the generated PLC code is validated before the machine is even built and reduces the real commissioning time dramatically.

In the provided use case the example will show the collaboration between the end customer and a Chinese OEM, where the machine was constructed in China and PLC code written in Germany with the integration into the CAD model. After the shipment of the machine to Germany the validated PLC code was downloaded smoothly and no structural changes were necessary. Needed changes were recognized beforehand in the Digital Twin model of the machine and communicated to the OEM during construction phase in order to amend the machine design.

The last Digital Twin use case will be the Digital Twin of performance with closed-loop innovation by aggregating data in a cloud and run analytics for further improvement of future production machines or prescriptive maintenance mechanisms.

As the reflow soldering process is the main energy consumer in a SMT assembly line, there is a high potential for cost reduction by significantly reducing the amount of energy needed. Melting the solder only needs a tiny percentage of heat, most of the energy is wasted to heat up the machine itself. If it would be possible to heat up only the solder joints to the required temperature the energy reduction will be substantial.

The crucial factor for such a process is to use a conductive heating material layer inside the printed circuit board (PCB) and generate the heat from inside by joule heating[2,3]. For this process it is necessary to have an electric current flow inside the heating material. This flow must be controlled as the heating layer is a carbon-based material and changes its resistance as a function of the temperature. The control circuit must be able to regulate the produced heat and generate a reflow like profile at the joints of every component on the PCB. The structure of the heating layer must be flexible as a result of having the possibility to adjust the amount of heat in a specific area of the PCB. So for a common PCB it will be necessary to have several connections from the current controller to the PCB.

In the joint research project “ERFEB” (Energy and Resource Efficient Production of Electronic Assemblies)[1], a current control unit will be designed and tested for different numbers of connections and different structures of heating layers to achieve a reliable reflow profile for a PCB soldering process.

As miniaturization trends continue in the electronics industry, System in Package (SiP) technology is gaining more and more traction. In many ways, some SiP modules are just surface mount technology in a high-density package. Component to component spacings are being driven even closer, pcb technology are migrating to package type substrates and more bare die are being used in these modules instead of conventional SMT (surface mount technology) packages.

This paper will discuss the flip chip process that has been developed for a 150μm pitch package, 10x10mm die size and greater than 3700 I/O full array solder flip chip. The test vehicle design will be shown, challenges that were faced during the process development, impact of warpage of the substrate on the flip chip yield and other factors that influence the successful assembly of these types of packages. This paper will describe processes from SMT and underfill and will touch on reliability test runs and the results of those testing.