The paper presents the development of an innovative recyclable and biodegradable PCB substrate material created to meet the stringent environmental demands of future electronic products. The substrate's technology readiness levels (TRL) are reviewed along with the current stages of testing and trial applications. The material addresses sustainability and environmental challenges by achieving carbon emission reductions of approximately 70% relative to conventional options whilst satisfying application appropriate standards of performance and usability. The product has been successfully trialed across many industry sectors, the paper details the achievement of equivalent critical performance metrics such as comparative tracking index, permittivity and UL flame rating with incumbent materials. The paper provides insights into how it offers OEMs, ODMs, and designers a viable pathway to significantly reduce carbon emissions in the PCB industry without compromising on quality or performance.

The increasing demands on electronic systems have led to the current trend of using chiplets instead of individual chips. In detail, this means that individual silicon components or functional units, which can also be developed and manufactured independently of each other, are combined to form a very powerful overall system. Since the miniaturization of semiconductor chips is a major challenge, minimizing the wiring length in the package by using denser and thinner connections is critical. The high number of inputs and outputs (I/O) in these high-density packages reduces the structural size of lines and spaces (L/S), and the quality of the interconnect can drastically affect the performance of the device. This paper presents the development of the necessary technology blocks for high-density redistribution layers required to realize such organic substrates.
The technology used is advanced semi-additive processing (aSAP) for large panels. This technology includes the use of dielectric layers such as Ajinomoto build up film (ABF) or similar, physical vapor deposition PVD seeding and additive electrolytic copper deposition.
Vertical interconnects can be produced by laser drilling, lithography using photo imageable or plasma with reactive ion etching (RIE). The process capabilities and limitations are discussed in detail.
Horizontal interconnects are produced by PVD seeding, photoimaging of resist masks and subsequent copper deposition, and resist and seed removal. Photo-imaging is an important step in this process. The development towards line and space structures targeting 5 μm and further 2 μm on large panels up to 510 x 515mm² is described in detail.

The IPC-1782 traceability standard is a key part of the IPC Factory of the Future ecosystem, providing a framework for ensuring trusted product and material provenance. The purpose of this standard is to assist material, component, and assembly manufacturers with maintaining product integrity throughout the supply chain.
It is important that all stakeholders in the supply chain have visibility into product movement, ensuring data transparency and validating the authenticity of packages as ownership changes throughout the process.
Provenance captures the origin and life journey of any asset—such as a component or a product—including its ownership history, custody, location, and more; covering all participants in the supply chain. Provenance data is crucial for meeting regulatory requirements, mitigating the risk of counterfeiting, supporting sustainable practices, and strengthening the resilience of supply chains.
This paper demonstrates the value of provenance data by presenting a standards-compliant Proof of Concept (PoC) that tracks the state and movement of assets through each Event Processing Task outlined in IPC-1782. It focuses on a real-world electronics manufacturing scenario and, as recommended by IPC-1782, utilizes an open-source, blockchain-backed provenance platform.
The PoC illustrates the value of combining external supply chain provenance with internal manufacturing traceability. By integrating with a Manufacturing Execution System (MES) and Supply Chain Management (SCM) platform, and leveraging industry standards like IPC-CFX and W3C’s PROV-O and PROV-DM, a seamless data flow can be established spanning both internal manufacturing processes and supply chain logistics to provide a holistic, end-to-end view of the product lifecycle, from raw materials to finished products.

For many years, metals have been used as thermal interface materials (TIMs), and until recently, the most common type of metal TIM were solder TIMs. Due to their high reliability and thermal conductivity, metal TIMs are excellent solutions for heat dissipation in electronic systems, especially for more challenging applications. Thermal conductivity and interfacial resistance are the most important properties of TIMs. With devices becoming smaller, consuming more power, and producing more heat, finding the right TIM becomes a highly critical step in any electronic systems application. Recently, liquid metal TIMs have gained popularity, especially for the thermal management of high-performance computing semiconductor applications such as central processing units (CPUs), graphics processing units (GPUs), and multi-chip modules (MCMs). Due to their fluid nature, liquid metal (LM) TIMs do not need to be compressed to maintain even contact, and they can accommodate imperfections in the neighboring components. The newest metal TIMs are made of liquid metal paste (LMP). LMPs are materials that still have gallium-based LMs as a key component, but they also have some additives that change their mechanical and/or thermal properties. The goal of those LMPs is to solve some of the issues that LMs have as a TIM.
The first part of this paper addressed pure metal LMPs, where all additives were metals. This second part will discuss new types of LMPs that combine gallium-based LMs with polymeric materials, such as polymer LM hybrids or polymeric liquid metal pastes (PLMPs). Polymer LM hybrids or PLMPs look like standard thermal pastes or thermal greases, but they have a high LM content. Just like the LMPs presented in the first part, PLMPs are less prone to oxidation and humidity, will have better performance in thermal cycling (-40/+125˚C) than LMs, and are electrically non-conductive* despite the high LM count used to create PLMPs. This paper addresses the challenges of the recommended dispensing process for the high-volume production of those PLMPs.
*PLMPs are electrically non-conductive at time zero (T0). More testing is required to prove that they will stay that way over time and that there will be no separation of LMs from PLMPs.
Key words: Bondline thickness (BLT), coefficient of variation (CV), dispensing, jetting, liquid metal (LM), liquid metal paste (LMP), polymeric liquid metal paste (PLMP), phase change material (PCM), solder paste inspection (SPI), thermal interface material (TIM), thermal test vehicle (TTV)

The advancement of high-frequency applications, especially for 5G technology, demands PCBs endure thermal shock during soldering while preserving signal integrity. Traditional copper foil surface treatments to improve resin adhesion increase signal loss due to surface roughening. As the industry adopts foils with extremely low surface profiles for improved signal integrity, methods are needed to correlate foil surface properties with signal integrity, and new methods of assessing the foil-to-low-loss dielectric bond are required. This iNEMI-organized project is addressing these challenges.
Scope of Work
The paper presents data obtained using non-contact profilometry methods, including the Developed Interfacial Area Ratio, (Sdr), and preliminary data from a Ruby Dielectric Resonator, measuring the effective conductivity of copper foils. These measurements are then correlated to microstrip insertion loss measurements on 12 sets of foil and oxide alternative treated surfaces. Two electrodeposited and one rolled-annealed copper foil grades, each with two roughness levels are included. Measurements are included of the foil surface bonded to laminate dielectric as well as the top side, treated with different levels of oxide alternative treatment.
The combination of extremely low-profile foils with low-loss dielectrics also raises concerns with thermomechanical reliability and bond-line conductive anodic filament (CAF) growth. The study will include a preliminary assessment of methods that might be used to evaluate these properties on laminates for new test method development. These findings may provide a foundation for a subsequent project.
This iNEMI project aligns with its PCB Roadmap and builds upon prior work performed by the HDP Users Group

Since its inception, the electronics manufacturing industry has developed methods to improve the efficiency of its many processes. One of the key methods developed and now a fundamental process is traceability.
Process traceability is used in virtually every step of the electronics manufacturing process, from solder paste printing to final inspection. Until recently there has been no way to trace hand soldering, rework, and repair processes. This resulted in a missing link in the overall electronics manufacturing process.
Hand soldering, rework and repair systems are now being designed to support process traceability. These new systems enable engineers to fully define the process. Operators then execute the process using an error proofing quality assurance mechanism. Once completed, all data relating to the process is stored, resulting in full traceability.
This new generation of hand soldering, rework, and repair systems must meet or exceed industry standards while also integrating with software that that performs three key functions: 1) allow for inputs to define the process, 2) command the soldering system and provide instructions to the operator, and 3) record all process data either within the software or export to a Manufacturing Execution System (MES). Communication will be done using common traceability protocol standards.
This advancement in hand soldering, rework, and repair enables full process traceability, providing an important bridge to this missing link in the overall electronics manufacturing process.

Enabling re-use of expensive BGA components with fast & high quality of BGA re-balling process can be a cost-effective solution.
It fits many electronic segments such as military, aerospace, computing, and communication. With operation models from R&D centers to EMS, RMA / repair centers.
High quality BGA re-balling process integrated into all-in one solution of dispensing and placement equipment. Seamlessly integrated sequence of flux deposition and balls (Spheres) placement with subsequent soldering process. The described automatic robotic process of re-balling does not require long setup or jigs and manual / professional processes to perform the job.

Industry 4.0 defined a vision for the factory where automation dynamically adjusts and adapts to its operational demands and to the products it is building. What has been overlooked is the complementary role humans have in the manual tasks they perform, whether it involves machining, assembly, inspection, test, or repair. In the digitalized factory these actions must be captured for real-time monitoring and reaction, as well as for historical record. Digital platforms and data standards, such as IPC-2581 (CFX), can be utilized without compromise for this purpose to reflect the work performed by people in as effective a manner as when done by machines. The primary objective is to contextualize these manual actions by linking them to specific products, locations, time stamps, and the underlying reasons for their execution, using a unified data model. By integrating human performance data with machine data, we can enhance operational efficiency, improve quality control, and foster a more collaborative environment between human operators and automated systems in the digital factory landscape.

Direct Digital Manufacturing (DDM) of additive electronics has gained considerable momentum in recent years due to the 3D design creativity that its additive materials provide. However, the same plastics that afford this creativity have low temperature limits, which hold back the circuit structure from high conductivity performance. Glass substrates are becoming increasingly interesting to performance seeking customers due to their smooth surfaces and higher temperature tolerances. While glass processing temperature (~400°C) outperforms that of plastics and FR4, it is still too low for optimal standard silver application (~850°C). Next-generation nanopastes present a promising lower-temperature solution to bring additive methods to glass substrates, offering excellent conductivity while achieving lower thick film resistance and smooth edge definitions. The methods developed in this work show that dispensed nanopaste on glass substrates gives superior DC and radio frequency (RF) performance, and unlocks a new class of high-performance glass Additively Manufactured Electronics (AMEs).
Silver nanopastes are often used as the conductive trace and interconnect material in AMEs for their suitability in microdispensing. Their conductivities are lower than their datasheet values, however, due to the low working temperatures of the plastic structures in AMEs, which often can go no more than 120°C. Silver nanopastes typically reach maximum conductivity at 250°C or higher. Experiments are conducted to compare silver nanopaste conductivity on traditional plastic AME substrates and glass substrates. A fully functional single layer circuit is then fabricated on glass. Design for manufacture rules and processes are compared between plastic AMEs, glass AMEs, and traditional PCBs.

In the quest for perfection within SMT printing, numerous factors such as print speed, blade pressure, and nano-coatings have been meticulously studied. Yet, the solvent delivery system—a critical component in maintaining high yields amidst diminishing aperture sizes—remains underexplored. This paper addresses the gap by examining the contact time of the underside solvent with the stencil during conventional wiping processes. It investigates how this interaction influences Transfer Efficiency and whether it can inform the development of new solvent formulations and new fluid delivery systems that are compatible with operators, environmentally safe, and suitable for equipment use. By delving into the printer’s fluid delivery system, we analyze how controlled volume and contact time, dictated by exposure duration, are pivotal in minimizing defects and maximizing yields. The findings aim to broaden the process window, ensuring consistent quality in an industry where precision is paramount.
Keywords: stencil under wipe, stencil cleaning, Under-stencil cleaning Chemistries, CPK