The physical reliability of a printed circuit board (PCB) is often seen as more important than having the best dielectric performance. Hence, a great deal of research and development has been put into testing various dielectric materials’ ability to survive in high-humidity, high-temperature testing without allowing copper to migrate between closely spaced features such as hole-walls. When copper migration does happen, it often occurs as dendritic type growths that form filaments, where a single filament can cause a short between two closely spaced copper features. This type of short is the result of an internal electrochemical migration (ECM), and can result in the formation of a conductive-anodic filament (CAF) [1] failure, or simply CAF for short. It is often assumed that anytime failures occur during high-temperature, high-humidity CAF testing, it is because of some shortcoming of the host resin system. However, in this study, we aim to show that an otherwise CAF-resistant resin system can be made to fail CAF testing if poor design choices are made and executed when building a test vehicle or other stack-up.

Woven glass fabric has been used in PWB laminates since the 1960s as a replacement for paper reinforcements. It complements the resin system properties by adding high tensile strength, dimensional stability, high thermal resistance, among other critical properties. Circuit design trends require glass type changes to meet microvia technology requirements, improve CAF, and enhance signal integrity. What can be changed now for improved laminate performance? Glass type composition, weave, and glass styles are one area of improvement. How does this affect the laminate performance from a short-term and long-term degradation perspective, specifically in reference to safety requirements?
The purpose of this project is two-fold: Measure PWB laminate long-term thermal degradation effects, which are associated with elevated normal use temperatures and the resulting loss of critical properties over the life of a product. Polymeric material performance due to degradation can be determined by measuring the changes in the electrical and mechanical properties to a predetermined level by long-term thermal aging (LTTA) testing.
The second objective is to measure the relative thermal index (RTI) value, which is an indication of the material's ability to retain a particular property (physical, electrical, etc.) when exposed to elevated temperatures for an extended period of time. Each index is related to a specific property and a specific thickness of the material. The electrical index is based on Dielectric Strength testing, and the mechanical index is based on Flexural Strength and Tensile Strength testing. These properties are considered leading indicators of laminate degradation and are used based on the ease of testing.

Printed Circuit Boards (PCBs) are essential components in modern electronics, serving as the backbone for electrical connections. The final finish of a PCB is crucial for reliable solder joint formation, manufacturing yields, and performance of the PCBA. As the industry has moved towards lead-free technology, fabricators have largely abandoned Hot-Air Solder Leveling (HASL). Instead, several alternative finishes - such as Immersion Silver (ImAg), Immersion Tin (ImSn), Organic Solderability Preservative (OSP), Electroless Nickel Immersion Gold (ENIG), and Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) - have become well established, each meeting fabricators' specific cost and performance requirements.
Choosing the right PCB final finish is critical for the performance and longevity of electronic devices. Factors such as cost, application, environmental considerations, and manufacturing capabilities should guide the selection process. By understanding the characteristics of each finish, designers can optimize their PCB designs for reliability and efficiency in their specific applications.
The recent introduction of the 5G mobile network has created a growing demand for smartphones, networking, and wireless connections, all of which require increased data flow. Consequently, reducing signal loss at higher frequency bandwidths is becoming vitally important. Additionally, with decreasing line spacing in new PCB designs, there is a growing need for those novel finishes. In this paper, we will present a detailed review of the final finishes currently available in the market, including newly developed options like nickel-free finishes.
Keywords: Final finishes, Surface finishes, Ni-free finishes, ENIG, ENEPIG, OSP, ImAg, ImSn

The iNEMI project on Artificial Intelligence (AI) Enhancement to Automated Optical Inspection (AOI) for Printed Circuit Boards Assembly (PCBA) has demonstrated the potential of AI technologies to improve the performance of AOI systems. By establishing common performance metrics and conducting rigorous experiments, the project provides valuable insights and recommendations for industry. The experimental evaluations demonstrated significant improvements can be achieved in AOI performance with the integration of AI technologies.
Computational efficiency and higher accuracy are among the main challenges of the recent computer vision base applications. Pre-trained Vision Transformers (ViT) have the potential to address those challenges by consuming a fraction of computational resources and achieving high accuracy for image recognition applications. Due to self-attention mechanism in global context, efficient scaling, adaptability to various tasks with minor architectural changes, a pre-trained transformer can perform well on image classification tasks compared to CNNs (Convolutional Neural Network) approach. For this work a pre-trained ViT Base 16, transformer was trained on smaller dataset containing about 2400 images of electronics generated within the iNEMI project on AI Enhancement to AOI for PCBA which were labeled as defective and non-defective. The model was tested on a separate dataset for testing. A hyperparameter fine tuning was performed on this model for an optimized learning rate and number of epochs where the model achieved a prediction accuracy of about 85% on the testing dataset. Compared to the alternative CNN models this model requires a lot less training images which significantly shorten the process of labeling, while achieving promising prediction accuracies.

Flexible hybrid electronics (FHE) combine flexible substrates with traditional electronic components to create flexible circuits, which reduce form factor and increase mechanical stability. Current manufacturing of FHEs typically relies on the photolithographic patterning of copper films on a suitable substrate, followed by the etching and removal of excess material. While these processes can provide nanometer resolution, they are naturally complex and require hazardous chemicals and expensive, specialized equipment. Herein, a novel process is presented that utilizes copper-plated Laser-Induced Graphene (Cu-LIG) to create high-quality, on-demand flexible electronics. This direct-write method of laser exposure to form the circuit greatly simplifies FHE production by removing the necessity for photolithography. The primary equipment for this process is a simple desktop computer network-controlled (CNC) toolset equipped with 450 nm, 7 W laser. The LIG precursor is modified with palladium nanoparticles prior to lasing, to provide surface catalytic sites for electroless copper deposition. Investigation of this process reveals a minimum laser fluence of 147 J×cm-2 to reliably initiate copper plating and coated structures exhibit sheet resistances of 149 mΩ/sq, which is several orders of magnitude lower than bare LIG. Full material characterization demonstrates a reliable process for creating functional, on-demand FHEs. Ultimately, the process is used to pattern a flexible operational amplifier on polyimide film and demonstrates the feasibility and reduced complexity of this method for scalable manufacturing of FHE.

As sustainability becomes a top priority at companies around the globe, OEMs and Printed Circuit Board fabricators alike are turning to their supply chains to assist in quantifying their greenhouse gas emissions through Product Carbon Footprint (PCF) analysis. The process of making Printed Circuit Boards (PCB) is resource-intensive, requiring significant amounts of water, energy, and chemicals, some of which are classified as carcinogens, providing fabricators with large opportunities to reduce consumption. With a comprehensive understanding of their products’ environmental impact through PCF analysis, supply chain stakeholders can evaluate methods to reduce their footprint while maintaining high standards of reliability and performance.
The process of making holes conductive is a critical step of the PCB manufacturing process. Historically, this has been achieved with electroless copper processing, though there are alternative methods available that show clear sustainability benefits while maintaining high reliability. Previous studies have shown large reductions in power, water and chemical consumption in the use-phase when utilizing direct metallization technologies instead of traditional electroless copper processes. The full benefits of direct metallization can only be realized if the products’ manufacturing process also demonstrates a lower environmental impact.
In this paper, we will discuss the environmental impact during the use-phase as well as compare the cradle-to-gate PCF analyses of multiple direct metallization processes to an electroless copper process utilizing the methods outlined in the ISO 14067 standard.

Interconnect Stress Testing (IST) is used to assess the reliability of microvia interfaces in printed circuit boards. To better understand the failure mechanisms, samples from different designs of experiments (DoE) test lots that failed during IST were prepared using the ion beam etching technique. Then, they were analyzed using a scanning electron microscope (SEM) and electron backscatter diffraction (EBSD). This study shows that specific manufacturing defects lead to different shapes in the IST curve. Some curves show a simple rise, while others display exponential behavior. This study analyzes the different curve shapes observed in IST to link these shapes to specific failure modes. Related causes for the different failure modes will be discussed. The objective is to determine how various interface structures influence the reliability behavior of the microvia, as observed directly in the IST curve.

With the development of electrification and digitalization in different fields, materials in electronic function units are also expected to work under exposed climatic condition as conventional structural materials Electrochemical migration (ECM) was considered as corrosion process due to water condensation. For ECM related failure, the whole process of ion migration and dendrite formation might take only few minutes if conducive conditions of ion stability exist in the electrolyte. For many years, the dendrite from the electrochemical migration was qualitatively investigated under the scope of mechanistic, structure, and elemental composition. However, none of the research could illustrate how many ions are required to initiate the detrimental point for electrochemical migration and how many ions are required to cause short circuiting by dendrite formation. This paper quantitatively demonstrates the whole process of the dendrite formation from initial dissolution of anodic material until the occurrence of short circuiting. The corrosion state of Sn based corrosion product at electrode was investigated using Raman spectroscopy. The droplet induced dendrite formation was directly analyzed using Inductive Coupled Plasma Optical Emission Spectrometry (ICP-OES) with 30 sec intervals of 5V/10V DC bias until failure occurred. Transmission electron microscopy (TEM)) was conducted, and the result illustrates the Sn semiconductive filament for the first time, which proposed an updated mechanism for short circuiting failure.

The increasing demand for higher signal density and miniaturization in electronic devices has driven the use of multilayer printed circuit boards (PCBs), which stack multiple circuitry layers to achieve complex designs. However, these conventional multilayer approaches restrict component placement to the outermost layers—top and bottom surfaces—apart from using embedded components which could introduce additional assembly and reliability challenges. This paper proposes a novel method utilizing 3D molded interconnect devices also known as mechatronic integrated devices (3D-MIDs) to create a three-dimensional PCB component stack, providing additional layers of usable real estate for component placement, thereby addressing the spatial constraints inherent to traditional multilayer designs. Various design features and form factors are evaluated to determine their effectiveness for different applications, with a focus on maximizing volumetric efficiency, mechanical stability as well as electrical and thermal performance of the system. The substrate material selection is analyzed to balance manufacturability and cost-effectiveness with mechanical and thermal properties through comprehensive mold flow analysis and thermal simulations. The paper also examines the compatibility of MID-based PCB stacks with state-of-the-art surface mount technology (SMT) manufacturing processes, including pick-and-place systems, and reflow solder processes through experimental analysis. The findings highlight the potential of MID-based PCB stacks to enhance PCB design by enabling more compact, and versatile electronic systems, suitable for a wide range of applications through its potential for a significant reduction in assembly time and overall complexity of the end product.

This paper presents a real-time, AI-driven defect detection system designed to enhance quality control in electronic assembly, providing manufacturers with precise, customizable screening parameters. The system utilizes a two-stage approach: an initial high-sensitivity detection phase that aligns with IPC-A-610 standards, followed by a secondary defect classification stage, activated only on approximately 200 defective parts per million (ppm). This configuration enables high-speed processing with minimal impact on computational resources, making it suitable for high-throughput environments.
The approach includes a “quality control knob,” allowing manufacturers to adjust defect thresholds, selectively target specific defect types, and apply tailored inspection parameters to different component classifications. This flexibility allows a balance between high-quality standards and production efficiency, reducing attrition rates and minimizing waste. For example, setting the quality threshold to meet IPC-A-610 standards results in a defect rejection rate of 207 DPM at an attrition cost of $0.62 per million components, while more lenient settings can reduce attrition to 59 DPM, costing only $0.18 per million components. This enables manufacturers to make informed trade-offs between quality and cost.
In addition to improving product reliability, the system reduces rework, scrap, and the environmental impact associated with production inefficiencies. Test results demonstrate the system's effectiveness in detecting diverse defects such as corrosion, foreign object debris (FOD), bent leads, and structural damage, allowing manufacturers to uphold stringent quality standards. This flexible, adaptive inspection method not only enhances quality control but also advances sustainability in electronic manufacturing by significantly lowering defect-related issues.