Continuous pursuits for higher data rate, larger network capacity, lower latency communication, and better energy efficiency have motivated the rapid development of high-frequency communication technologies in recent years. Owing to the skin effect, the alternating electric current (AC) tends to distribute to the outer of a conductor in high-frequency transmission, such that the surface roughness of interconnects becomes an indispensable factor of the signal transmission characteristics. The focus of this study was to quantitatively investigate the effect of Cu-foil roughness on the signal transmission characteristics at mmWave frequency bands. The signal loss on differential striplines with different Cu-foil roughness was simulated by the Groisse and Huray models through using a 3D electromagnetic simulation software (HFSS). Furthermore, experimental measurements were conducted by using a vector network analyzer (VNA) to characterize the signal characteristics arising from different surface roughness, so as to validate the numerical simulation results. This quantitative analysis not only advanced our own fundamental knowledge in surface modification of the high-frequency materials but is greatly beneficial to the development of the 5G communication technologies. Detailed analyses on the high-frequency signal transmission performance of the differential striplines made of different Cu foils will be presented in this paper.
Keywords: 5G, HFSS, Roughness effect, Cu foil, Huray model, Groisse model.

Laser depaneling is a relatively clean separation process but nevertheless the knowledge of potential influence factors on the technical cleanliness is of central importance to find the optimal layout for demanding applications. Especially in industry sectors such as automotive and medical technology, technical cleanliness is one of the key requirements to ensure a reliable and secure function of the PCB and consequently the product. This paper presents an in-depth analysis of the particle contamination for different laser variants, cutting strategies and panel designs. Therefore, the panels have been processed with a tab and full cut as well as with the target for maximum performance and maximum cleanliness of the cutting edge on three different laser systems. In addition, design changes have covered different material thicknesses of the panel. The particle examinations comprise a particle extraction and subsequent analyses with optical light analysis as well as optical particle counting. The results of the measurements are verified against standards for technical cleanliness in the automotive (VDA19.1/ISO 16232) and medical industry (USP 788). This paper is examining in how far these fundamental standards can be achieved for all observed laser variants, designs and cutting strategies by identifying the largest metallic and non-metallic particles as well as counting and grouping the particles regarding their size. In addition, the authors are investigating the correlation of those variable factors and their impact on the level of technical cleanliness, allowing recommendations for the design of printed circuit boards to be derived from it.

The multilayer PCB is prone to poor expansion and shrinkage due to the influence of high temperature and high pressure during lamination process, which may cause risk of abnormal quality. The traditional method is to estimate the compensation value manually, which has low efficiency and great influence of human factors. The quantitative relationship between the compensation value and the expansion and shrinkage value is also unclear. In this context, this article establishes the base material expansion and shrinkage control index system, and uses descriptive statistics, correlation analysis, scatter plot and trend line analysis to carry out qualitative and quantitative analysis on the influencing factors and compensation ratio of expansion and shrinkage for different layers PCB, so as to effectively control bad expansion and shrinkage to improve production efficiency.

In laptop and tablet CPU/GPU applications, package thickness tends to be thinner since it brings lighter weight, lower product thickness, and shorter interconnection distance. To decrease package thickness, several parts of the package structure can be considered, such as bump height, ball height, die thickness, and substrate thickness. This study focuses on the thickness reduction of the substrate core.
The copper-filled plating technique will be used to fill the through hole instead of resin plugging when the substrate core becomes thinner, from over 400 μm to below 200 μm. However, during the copper-filled plating process, through hole opening tends to be closed earlier than through hole center due to the nature of electroplating. Consequently, voids are easy to form, causing delamination and crack risk during package reliability tests when the void area is too large or the barrel thickness is not enough. This research mainly explored copper distribution at the early stage of plating since it is important for minimizing void size and controlling barrel thickness. Various combinations of flow rate and current density have been designed to have different throwing powers and interactions with additives. From the results, uniform copper distribution and secured barrel thickness with low current density and high flow rate conditions were demonstrated. At the same time, successful inhibition of copper deposition around the through hole opening lets plating chemicals reach the center of the through hole. Therefore, void size can be minimized to lower the risk of package reliability failure.

The reflow soldering performance of polymer aluminum electrolytic capacitors have a direct impact on their electrical performance. By analyzing the mechanism of capacitor bulges, improve the composition materials and production process, to enhance the high-temperature resistance performance, and reduce the risk of capacitor bulges.

Flip chip BGA, interconnect with semiconductor chips and mainboards, to serve the interconnection of electronic products. This paper is about the study of one of the important warpage modulator in flip chop BGA product. When flip chip BGA interconnects with semiconductor and mainboards, assembly problem can occur by substrate warpage caused by thermodynamic behavior and incoming substrate warpage, CTE mismatch and other noise factor. During assembly process, unexpected warpage behavior can make open or short problem. The warpage of flip chip BGA is made by thickness imbalance, thermal process, mechanical damage and assembly condition. In advanced technology of manufacturing process, all process apply full automation and optimize to thickness control and it can improve a thickness imbalance, thermal behavior and mechanical damage by machine. But in sudden case of machine trouble, operator need to take off the panel by manual and it can make the soft touch of the panel. This study is about how soft touch can affect flip chip BGA product warpage. In case of horizontal soft touch of the panel, the combination of gravity force and product’s weight can make panel warpage and it can make substrate warpage. The thermal reflow test result shows that the increase of soft touch shows increase of abnormal behavior by 0 → 7 →16 →22 EA, when soft touch 0 → 1 → 2 → 3 times increase. This result shows soft touch of the panel can make unexpected assembly open or short problem. From this simple experiment, the effectiveness of soft touch is most important when flip chip BGA manufacturing process.

In the pursuit of ever finer lines and spaces to advance technology's power and efficiency, the substrate and substrate-like production processes must adapt to meet these demands while carefully considering procedural interdependencies. Traditional flash etching, essential for removing the seed layer after pattern plating in Semi-Additive-Processing (SAP) and advanced Modified-Semi-Additive-Processing (aMSAP), presents challenges like undercuts, increased roughness, and trace geometry distortion. These issues are particularly pronounced as conductor size decreases. Hence, the primary objective is to achieve a high etching rate on the seed copper while minimizing damage to the conductor, often referred to as the etching ratio.
However, economic constraints introduce an added layer of complexity. More viable base chemistries, such as ferric sulfate etchants, tend to be costlier in terms of raw materials and dosage requirements. Therefore, cost-effective regeneration measures become imperative to mitigate the adverse commercial impact associated with these solutions. Additionally, specific additives are required to control the etch rate, etch ratio, and working window of the overall flash etching process.
In this paper, we introduce a novel ferric sulfate differential etchant designed to address these multifaceted challenges. We delve into its function and performance, offering insights into how it can serve the substrate and substrate-like production processes by providing an effective, cost-efficient, and environmentally friendly solution to meet the evolving demands of modern technology manufacturing.
Key words
Flash etching, differential etching, seed layer etching, mSAP, Modified-Semi-Additive-Processing, SAP, Semi-Additive-Processing

The protection of metallic substrates from reactive environments is necessary for semiconductor packages, which are mainly made of copper metal. Conventionally, plating with novel metals such as silver or gold is used. In this case, due to the high cost of novel metals, the process becomes complicated, such as plating only the wire bonding part. In addition, since plating is carried out using a wet process, it requires a space for storing the plating solution. This leads to the disadvantage of increasing the facility area needed to perform a continuous process.
Recently, graphene used for surface protection of metals has been grown using chemical vapor deposition (CVD) at 1000 ℃. However, this method has several negative effects, including size deformation and reduction in hardness of the metal substrate due to the high-temperature synthesis.
Here, we demonstrate the growth of few-layer graphene films using low-temperature plasma-enhanced chemical vapor deposition (PECVD) to protect the metallic substrate from air oxidation without causing any physical degradation to the substrate. The structural characterization, focused ion beam (FIB)-Scanning electron microscope (SEM), Raman spectroscopy, and X-ray photoelectron spectroscopy (XPS) studies show that metal surfaces are well protected from oxidation even after an accelerated oxidation evaluation of 85°C and 85% RH for 5 hours.

This study is part of a series of papers on mitigation of voids in solder joints. Voiding is an ongoing concern for printed circuit board assembly (PCBA) manufacturers. As bottom terminated components (BTCs) become increasingly popular, the potential for voiding in solder joints has increased. Voiding limits are often imposed on PCBA manufacturers. These voiding limits lead manufacturers to find ways to mitigate voiding.
There are two major mechanisms for void formation. The first mechanism is gas entrapment in the solder joint. Gasses come from volatile materials in the flux, air gaps in the solder paste print, and from the PCB and components. The second mechanism for void formation is incomplete wetting or spread of the solder. When the solder alloy does not completely wet both the PCB pads and component leads, gaps remain in the solder joint.
This study is a continuation of work on voiding with respect to solder alloy and stencil design for quad-flat no-lead (QFN) components. The solder alloys tested include Sn63/Pb37, SAC305, SnBiCuNi, SnAgBiCu, and Sn37BiX. A water-soluble Pb-free solder paste flux and SAC305 reflow profile were used. The stencil design was varied on the QFN thermal pads to determine how gap size affects wetting of the solder alloy. Wetting behavior and gas entrapment were correlated to voiding for each solder alloy. The data for both parts of the study was summarized, and recommendations given to help “Fill the Void.”

ETS (Embedded Trace Substrate) is one of advanced substrate design that enable to make fine width and space. The Cu trace open defect on ETS layer (L01) revealed by this OSP micro etching is non-detectable defect mode because OS test (Open-Short test) to detect this kind of defects is done before OSP process. The reason of OS test prior to OSP process is to prevent damage on Cu surface coated with OSP caused by OS test pin mark. OS test can be done after OSP process to detect this defect. But there was no specific study or approach regarding solder joint quality with OS test pin mark. TCNCP (Thermal Compression bonding with Non Conductive Paste) solder joint quality associated with OS test pin mark on ETS layer coated with OSP is investigated. This study demonstrates that Cu trace open on ETS layer generated by OSP micro etching can be detected by OS test prior to OSP process, and it is revealed that TCNCP solder joint quality can be worse due to increased NCP (Non Conductive Paste) entrapment as the number of OS test retrial times are increased.