The datacenter continues to demand increasingly higher component data rates to satisfy growing application requirements. Efforts are underway, as illustrated by the IEEE 802.3dj objectives[1], to continue the ethernet roadmap up to 1.6 Tb/s to enable this. Providing 1.6 Tb/s bandwidth requires individual lanes operating at a data rate of up to 224 Gb/s, with each lane’s Nyquist frequency extending up to 56 GHz. While several devices in the datacenter will need to support these data rates, the ethernet switch presents several unique challenges to the printed circuit board (PCB) due to the large number of signals required at the maximum data rate and the substantial power requirements.
In this paper we utilize an ethernet switch PCB design to walk through the challenges of implementing 224Gb/s signaling. We illustrate how this difficulty is compounded by the need to simultaneously meet electrical performance, manufacturability, and reliability goals within the PCB along with consideration for cost of the platform. Simulations will be used to illustrate the design process applied to meet the desired performance of <15 dB insertion loss at 56 GHz, and measurements are presented to demonstrate that these targets are achievable. We will also discuss scalability of this performance to 448 Gb/s. Finally, we outline several areas related to PCB materials where IPC/Industry efforts either need to be initiated or accelerated to enable even higher data rates in the future.
Key Words: High Speed Input/Output, Printed Circuit Board, Signal Integrity, 224 Gb/s, Roughness

In addition to manufacturability, performance, reliability and cost, environmental impact increasingly becomes a design driver for printed circuit boards and assemblies. A prerequisite is the availability of design-dependent data on energy consumption, water use, waste generation and material use during PCB manufacturing. Using the published parametric Life Cycle Inventory model for PCB manufacturing, this paper explores the environmental impact of certain design choices: board dimensions, build-up (number of layers, Cu thickness), and surface finish and their influence on energy consumption, water use, waste generation and material use in PCB manufacturing.

Warpage determination for ball grid array (BGA) packages require measurement of the surface containing solder balls. Balls can be sheared, and the surface painted. Surface damage can alter the substrates surface causing local distortions. With packages becoming smaller and thinner, physical shearing of solder balls is becoming impractical. Alternatively, paint can be applied without physically removing the balls. Balls are removed digitally in a rigorous process of pattern matching through numerous acquisitions obtained to recreate the reflow profile. Alternative methods to obtain warpage values without having to remove balls or paint the BGAs surface are explored. The first method examines measuring the unpainted ball side through Digital Fringe Projection (DFP) and digitally removing balls based on pixel saturation. The second method measures the packages unpainted top side through Shadow Moiré (SM) and correlates a warpage value to the ball side.
Making a valid comparison between top and bottom surfaces will require understanding how warpage impacts the components through multiple repeat thermal cycles and optimizing run conditions to obtain equivalent coplanarities over temperature profiles between DFP and SM. Due to the difference in data density between these two methods, comparable smoothing parameters must be selected to ensure optimal data quality and equivalent area comparison. This paper assesses how well the top and bottom surfaces correlate to each other and explore how factors such as physical dimensions or top side features may impact results.

The increasing use of larger Ball Grid Arrays (BGAs), ceramic packages, and Wafer-Level Chip Scale Packages (WLCSP) to enhance device functionality requires improved reliability in challenging environments, such as automotive printed circuit board assembly (PCBA). The selection and evaluation of underfill materials have become more complex due to advanced processing requirements driven by innovative package technologies and stricter design specifications. Each advancement requires a thorough reevaluation of reinforcement material choices.
To meet stringent reliability standards for thermomechanical performance, vibration resistance, and drop shock resilience in advanced devices, high-reliability solders and polymer reinforcement materials, such as Edgebond and underfill, are increasingly utilized.
Two primary reinforcement strategies are employed: using flowable underfill to fill all gaps beneath the device or applying no-flow reinforcement (Edgebond) material to secure only the edges. The selection between these methods depends on reliability needs, device construction, and manufacturing throughput.
This paper presents comparative study of high-reliability alloys in conjunction with underfill and Edgebond materials designed to enhance the reliability of conventional BGAs and WLCSP. The evaluation includes analysis of components with differing warpage characteristics, pitches, and sizes to assess their mechanical and thermomechanical performance.
The findings will show the effectiveness of different reinforcement strategies in improving the reliability of BGAs and WLCSP under diverse environmental conditions. By providing insights into the performance of advanced materials, this research aims to advance robust electronic packaging solutions essential for high-reliability applications in harsh environments.
Key words: BLR (Board level Reliability), Reinforcement, Underfill and Edgebond, BGA, Drop Shock, Thermocycling.

A variable angle print head offers significant advantages in screen printing, allowing the user to adjust the squeegee angle of attack with precision to achieve optimal results. This feature is particularly beneficial when working with different types of surface features, as it enables the user to customize the squeegee angle to suit the specific requirements of the job.
Traditionally, the squeegee attack angle was determined by selecting a pre-defined blade (squeegee) with a fixed angle. The standard holder angles available are typically 45 and 60 degrees. This approach required process engineers to conduct Design of Experiments (DOE) to ascertain the optimal attack angle for a particular application. Once the angle was selected, it could not be altered without physically swapping the holder with one featuring a different angle. This process increased the risk of installing incorrect squeegee holders, potentially leading to printing errors.
This paper explores the benefits of having the capability to change the squeegee attack angle without changing the blade holder. It describes the technical aspects of how this was achieved and presents the experiments that were conducted to validate the effectiveness of the variable angle print head.
The variable angle print head is a breakthrough in screen printing technology that offers several key processes. First, it eliminates the need for multiple squeegee holders with different angles, reducing the risk of incorrect holder installation. Second, it provides the user with the flexibility to adjust the squeegee angle ‘on-the-fly’, allowing for quick and easy optimization of the printing process. Third, it enhances the overall efficiency and productivity of screen printing operations.
The paper begins by introducing the concept of the variable angle print head and its significance in screen printing. It then explores the challenges associated with traditional fixed-angle squeegee holders and how the variable angle print head addresses these issues.
Furthermore, the paper presents an experimental setup and procedures that were employed to evaluate the performance of the variable angle print head. These experiments aimed to assess the impact of different squeegee angles on print quality, productivity, and overall process efficiency. The results of these experiments are presented and discussed, highlighting the significant improvements achieved by using the variable angle print head.
The paper concludes by summarizing the key findings and discussing the potential implications of the variable angle print head for the screen printing industry. It emphasizes the benefits of increased flexibility, improved print quality, and enhanced productivity that can be realized by adopting this innovative technology.

Metastable solder pastes offer a compelling advancement in low-temperature soldering, providing the capability to form robust metal interconnects at temperatures significantly lower than those required by traditional solder alloys. This innovation is especially crucial for next-generation electronics, where high processing temperatures can compromise the integrity of materials, structures, and overall performance, such as in package-attach and flexible hybrid electronics. In this study, we developed supercooled solder pastes made from core-shell bismuth-tin (BiSn) particles to achieve solder interconnects at temperatures below the alloy's melting point. Notably, the reflow of these supercooled BiSn pastes was successfully performed in a standard inline nitrogen reflow oven, with a peak temperature of 125°C, which is 40°C lower than conventional profiles for this alloy. Cross-sectional analysis reveals that even at this reduced temperature, sufficient intermetallic compound formation occurs, ensuring reliable connections. This paper highlights progress in process development and providing insights into practical application guidelines for future electronics manufacturing.

An electrolytic plate ultra-thin gold (UTG) over 2.5 to 5 microns(μ) pure nickel is an economical and environmentally friendly printed circuit board (PCB) finish, tested over 100,000M2. UTG was tested for solderability under double stress of an 8hour heat and humidity test followed by 2X IR reflow passes. A test lot of 100,500 plated through holes, with 1 to28 nanometre (nm) gold thickness, wave soldered with SAC leadfree solder, showed 99.93% holes completely filled.
UTG with 5 nm gold thickness, showed a bond pull strength is 6.75gf for aluminium wire (Al) bonding and no increase of resistance after 1 million membrane keypad operations. At 14 nm thickness, the gold wire (Au) bond pull strength averaged at 8 gf.
The manufacturing process is standard till PCB panel outer layers pattern copper, followed by an electrolytic nickel layer of 2.5 to 5μ on copper. Secondary imaging is done to cover all non-solderable and non-contact areas, to reduce the gold plating area. The panels are then plated with gold of 5 nm or as required, and etched. Overhang of 2.5 to 3 μ on a 5 μ base copper is achieved.
At 5 nm gold thickness, it uses 90% less gold than consumed in electroless nickel-immersion gold (ENIG) process. It reduces chemistry/pollution treatment costs by eliminating the ENIG processes of tin plating/de-plating, activation, electroless nickel, and immersion gold. The reduced gold consumption of this finish of 90%can save more than 1 million Tons greenhouse gasses per annum by substituting ENIG.

Miniaturization has exacerbated the issue of electronics failure due to humidity by reducing the spacing between components, increasing the possibility of droplet bridging to create pathways for Electrochemical Migration (ECM) under operational voltage. Additionally, the trend toward higher operating voltages, often exceeding 400V, has led to increased possibility of Anodic Migration (AM) and corrosion product growth from the anode.
This study aims to understand the failure mechanisms under high voltage (>100 V) and condensing conditions, compared to dendritic growth at lower biases (e.g., 10 V). Tests were conducted with PCB laminates of bare copper pads in a climatic chamber, maintaining a constant humid environment (95% RH and 25°C) and cooling down to temperatures below the dew point. Droplet morphology was recorded and analyzed using an in-situ digital microscope under condensation and applied bias. SEM-EDS was used to analyze corrosion product and chemical composition.
The study provides a comprehensive understanding of the combined effects of high voltages and water layer formation on ECM, AM, and corrosion product growth in high-powered electronic devices.

Automated optical inspection (AOI) systems are commonly applied for in-line quality control of through hole technology (THT) solder joints. However, these systems usually rely on conventional image processing, often leading to high pseudo error rates and extensive workloads during subsequent manual inspection. Deep learning approaches have shown promise in reducing pseudo errors by classifying solder joint images flagged as defective by AOI systems into two classes: real defects and pseudo errors. Yet, their performance is limited by the availability of sufficient local training data, and while cross-company data sharing could address this issue, it remains constrained due to privacy concerns.
Federated learning (FL) offers a promising solution by enabling collaborative model training across companies without the need to share raw data, thus preserving data privacy. This study evaluates the application of FL for THT-AOI image classification, specifically addressing common FL challenges such as divergence of local model updates and performance decay under non-independent and identically distributed (non-IID) client data. Therefore, local, centralized and federated learning are compared based on real and artificially separated data under IID and non-IID conditions.
Our results demonstrate that convolutional neural network (CNN)-based FL can be effectively applied for THT-AOI image classification, achieving training stability and model performance comparable to centralized learning. By implementing FL, we reduce AOI pseudo errors by an average of 23.6% on an aggregated test set containing heterogeneous data from multiple electronics manufacturers, significantly lowering the need for manual inspection. This represents a 12.1% relative improvement in pseudo error reduction over local learning, with both approaches maintaining a controlled error slip rate of 1.0%.