A phased array Antenna-in-Package (AiP) has been developed in an applied research collaboration between several companies. The AiP is designed and manufactured using a highly integrated packaging technology and is targeted for use in 6G Base Stations (BS) and User Equipment (UE) at 92-100 GHz for Joint Communication and Sensing (JCAS). Instead of using traditional chip and wire-bonding, or flip chips, the 6G AiP utilizes a 3D Cu-plating technology for die-to-die and layer-to-layer interconnects. This novel package technology comes with significant challenges from a design, manufacturing, board assembly, underfill, and reliability point of view.
This paper describes the board assembly related requirements on the package, board assembly- and underfill challenges, warpage and solder bridging mitigation actions, Board Level Reliability (BLR) test results, and finally shows the successful assembly results of the first functional AiP sample.

The integration of artificial intelligence (AI) in automated optical inspection (AOI) systems for printed circuit board assemblies (PCBAs) and semiconductors has garnered significant attention, driven by the need for improved accuracy, speed, and consistency in defect detection. Traditionally, specialized models are trained to address specific application tasks, such as defect detection or classification. However, inspecting a complete product often requires the application of multiple models, presenting challenges in training, maintenance, and scalability.
This paper introduces a novel universal deep learning model designed to segment AOI images for both PCBA and semiconductor components, offering a more robust and adaptable solution for defect detection. Experimental results demonstrate that the proposed model performs effectively across both PCBA and semiconductor AOI tasks, highlighting its versatility and potential for streamlining inspection processes. In addition, this segmentation model can also facilitate auto-programming in a high-mix low-volume production environment

Laser depaneling is driven by the clear industry trend to further improve performance and thus the cost-benefit ratio with ever more powerful lasers. As a result of this development, laser processing is being used in an increasing number of applications. Alongside this trend is the challenge of compensating for the additional power and associated increase in thermal energy, e.g. via appropriate deflection technologies.
Therefore, this paper presents an extended analysis of the proprietary temperature investigations of FR4 material during laser depaneling with higher laser powers combined with the use of advanced deflection technologies. In accordance with the previous examinations, the temperature measurement was carried out by using Type-K thermocouples applied in non-plated through holes. These thermocouples have been positioned at varying distances with a regular interval of 100 micrometers to the cutting channel. Thereafter, the temperature was measured for each distance during the ablation process through base material and partial copper layers. Based on these values, a temperature behavior model can be derived using statistical methods. The Target of this paper is a comparison to the previous investigation results and to examine if the temperatures with increased laser power are still below the liquidus temperature of tin/silver/copper alloy, even for the smallest distances. In addition, an optical inspection based on microsections is conducted to analyze potential heat affected zones and potentially discolorized surfaces. Furthermore, the authors are investigating the possible correlation between laser power and deflection technologies and their impact on temperature levels measured on the substrate material.

With the development of high-speed PCB, the control requirements of signal transmission for via stub are more and more strict. The back drilled metallized stub has to be controlled within the best and tighter range. In order to enhance the wiring density and reliability, it is often necessary to plug the signal vias, or plating over filled via (POFV). And this often results in voiding defects at fixed areas of resin plugged back drilled holes. This paper explores the causes of voiding in resin plugged back drilled holes by modeling and analyzing the stress of resin curing and thermal expansion in plugged holes, the structure of back-drilled holes, and the material properties. The experiment indicates that the smaller the back-drilled hole diameter, the shallower the back-drilled depth, the more isolated the back-drilled holes, and the greater the water absorption of the material, the more likely it is for voiding to appear at fixed areas of resin plugged back drilled holes. By prolonging the drying time before plugging, the incidence of voiding could be effectively reduced. This paper demonstrates that when the drying time of a certain material (B) before plugging is prolonged from 2 hr to 5 hr, the voiding defect rate of resin plugged back-drilled holes is reduced from 8.23% to 1.56%.

High-speed product segments, such as servers and network switches, are rapidly increasing data rate requirements in the electronics industry. With bandwidth requirements doubling every generation, tighter signal integrity requirements are crucial to minimize signal loss across high frequency channels.[1] To support the signal integrity requirements for these high-speed signals in printed circuit boards (PCBs), plated through hole (PTH) vias are drilled from PCB using a back-drill process. The back-drill process involves using a larger drill diameter than the PTH via to drill to a specified depth, resulting in a reduced via stub length. Reducing the via stub length limits the signal delay and reflection, which improves signal performance.[2] Currently, the back-drilling capabilities in the PCB industry have manufacturing limitations regarding how far via stub lengths can be reduced and controlled. Advancements in the back-drill process have been adopted to drive tighter stub length control, such as contact drilling, drill depth mapping, and camera-assisted depth drilling. As the industry explores and develops advanced back-drill technologies, it has been discovered that other techniques, such as balancing layer copper (Cu) density and alternative via stub processes, can enable tighter via stub length control. This publication provides insights and recommendations for meeting high-speed product segments by reducing via stub lengths below 150μm with advanced via stub processes. Along with process recommendations, this publication is a call-to-action for the PCB industry to address the challenges and limited metrology solutions for via stub length control.
Key Words: High-Speed Signals, Printed Circuit Board, Back-Drill, Via Stub Length, PCB Copper Density

Spring-loaded test probes for in-circuit or functional test are not new. However, with modern applications those designs have evolved a lot over the years. A traditional test probe consists of a spring, a plunger and a barrel = 3 components. This, however, may not be adequate anymore to perform certain kinds of tests, for example an RF/Wireless test with strict impedance matching requirements and a test frequency of 20 GHz or higher. Modern test probes can have thirty individual components or even more, and are highly complex with regards to its internal design, even though from the outside the parts still may look like a very simple test pin. For this presentation, we first look at the history of test probes. How did the parts look 30 years ago? What were the requirements back then, and what are we dealing with today (such as for example no clean boards with lots of flux residue or OSP organic surface preservative residue? We discuss the basic design of the test probe and then take it a step further and go deep into several applications which include RF&Wireless test, battery cell and module/pack test, advanced PCBA test, wire harness test and more.

A complex Printed Circuit Board (PCB), such as those in advanced electronics can house 500 to 1500 components. High-end systems like servers or telecommunications equipment can have thousands. Proper control of the reflow soldering process is essential to ensure good solder joints and to avoid defects. The thermal profile of an assembly is a critical parameter in reflow soldering. However, the thermal profile only measures 6 to maximum 20 spots on the assembly out of the thousands defect opportunities. The accuracy of the thermal profile depends on the thermocouple attachment and the accuracy of the loggers and devices.
Real time temperature profile systems are available. These systems use temperature sensors inside the reflow oven to generate virtual profiles of the printed circuit boards with network software for data sharing and traceability. This data can be combined with Solder Paste Inspection (SPI) and Automatic Optical Inspection (AOI) for defect analysis and process optimization.
In this paper the accuracy of the virtual profiling is verified. The impact of reflow oven deviations of fan speed and temperature on thermal profiles and virtual profiles are investigated in a Design of Experiment. The repeatability and consistency of different data loggers are defined in a Gage R&R study. Next generation reflow ovens will have different convection rate settings for individual zones. This will impact the thermal profiles and experiments show the variation on the virtual profiles. Is the virtual profile still valid when fan speeds are changed or start to drift?

The trend of miniaturization of electronics requires the creation of Ultra-high-density solder joints. Semiconductor manufacturing, flip chip, package-on-package (PoP), system in package (SiP), and miniature components like 0201M (008004 Imperial) may require printing through stencil apertures of 100-150 μm (4-6 mils) or less in size. Creating these miniature solder joints requires an optimized solder paste printing process and the use of IPC Type 6 (5-15 μm) [1] or smaller solder powder sizes.
Solder paste printing performance was studied using various stencil designs, step-stencil thicknesses, print parameters, and solder paste technologies. The test printed circuit board (PCB) included many challenging UHDI components. Printing performance was evaluated using solder paste inspection (SPI). The data was compared, and recommendations were made for successfully printing these ultra-high density soldering applications.

Our contribution concerns advances in electronics design software, achieved by linking popular Electronic Computer-Aided Design (ECAD) and full-wave electromagnetic (EM) simulations (here, with our in-house conformal Finite-Difference Time-Domain method). We have developed a module that integrates with the EM software and overlays within 3D CAD by accounting for the required wavelength resolution across various materials, while avoiding unnecessarily small mesh elements and simulation time-steps. For example, E-type mesh-snapping planes are set along edges of metallic bodies, while Finite-Difference Time-Domain (FDTD) elements are deformed and merged into conformal ones, to preserve simulation stability without time-step reduction. Thereby, we have combined the technical merits of ECAD geometry handling, Finite Element Analysis (FEA) flexibility is representing arbitrary shapes, and FDTD outstanding computational efficiency in simulating electrically large circuits over a wide frequency band.
The relevance of our contribution extends further beyond the EM project definition and analysis. Namely, the integrated software supports optimization and parameter sweeps, broadening its applicability for engineering applications, which will be illustrated in our talk based on microstrip line example.

Manufacturing defects in printed circuit boards (PCB) can significantly impact the quality, reliability, and cost. The design for manufacturing (DFM) process can help identify such errors before production. This paper highlights the best DFM practices, focusing on trace width and spacing, via design, material selection, stack-up preparation, solder mask clearance, and production documentation. It also addresses key manufacturing issues like annular ring breakage, warpage, copper slivers, and solder bridging. The paper also emphasizes the importance of early collaboration between PCB designers and manufacturers, which can significantly improve the DFM process and reduce design iterations.