There is a global consensus that the environmental impact of electronics needs to be reduced. The first step towards this goal is identifying the environmental hotspots in electronics manufacturing, usage and potential recycling. Quantification of the impact of electronics manufacturing is a prerequisite to this assessment. This study focuses on a vital part in the supply chain of electronics: the production of the printed circuit board (PCB). Available datasets containing energy consumption, water and material usage and waste generation during printed circuit board manufacturing are often static and consider only limited design variations. Due to the lack of better alternatives, these Life Cycle Assessment (LCA) datasets are used as generic drop-in replacements for any type of printed circuit board. This paper presents a design-driven parametric approach to model the energy consumption, water, chemical and material usage and waste generation of PCB manufacturing. This methodology is combined with a simplified method for data collection by the PCB manufacturer. The validity of the model is demonstrated by benchmarking against available LCA datasets as well as through demonstrating the influence of design choices such as layer count, routing density, PCB dimensions and type of surface finish. In addition to LCA practitioners, the model can be used by PCB manufacturers to calculate their energy consumption or water usage for their environmental impact reporting needs. Furthermore, it allows to identify hotspots in the production flow for environmental impact reduction purposes.

Flux which facilitates fine bump development and bump pitch was developed. The purpose was to achieve fine bump and bump pitch by securing rheological properties that are similar to, or an improved version of, mass-produced flux. To achieve the goal, the rheological properties of the flux had to be modified, so that solder paste could easily slip through a metal mask to form a fine pitch The ultimate focus was to develop a flux with an initial viscosity between 200~350 Pas and a thixotropy index (TI) higher than 3.0.. In this study, it was discovered that the realization of fine bumps is facilitated by a fluid with high elasticity, encompassing the crossover point (COP), storage modulus (G'), and loss modulus (G''). It was found that the key factors are the initial viscosity, thixotropy index (TI), and occurrences of COP.
In conclusion, the desired rheological properties were achieved in the composition of sample-09 (SP-09). In combination of SP-09 with initial viscosity 275 Pas, TI higher than 3.0, and COP higher than 100 Pa, it successfully printed using the mask with 26 um metal mask opening (MMO). It was expected that the reduction of bump pitch beyond the limit of current mass production capability and the establishment of strong competitiveness through material dualization would be facilitated by the new flux.

Thermosetting epoxy resin is widely used in electronic materials for its excellent insulation, heat resistance, mechanical properties, chemical resistance and processability. However, the non-metallic part of printed circuit board (PCB) is difficult to be degraded and recycled due to the infusibility and insolubility of the traditional thermosetting epoxy polymer. In this paper, a novel halogen-free degradable copper clad laminate (D-CCL) was developed and processed into degradable PCB (D-PCB). The main properties of D-CCL and the reliability of D-PCB were tested. Then，the non-metallic part of the degradable material was degraded by chemical treatment in the degradation solution, and the feasibility of recycling the degraded recycled mixture in composite epoxy material (CEM) was investigated. The results showed that the main performance of the novel D-CCL could meet the performance requirements of conventional halogen free FR-4. The processability and reliability of D-PCB were comparable to that of the conventional FR-4 counterpart. Both the liquid and solid contents separated from the non-metallic degradation mixture could be recovered and applied to manufacturing of CEM, such as CEM-1.
Key words: Epoxy resin, Degradable, Recycling, CCL, PCB, CEM

2.5D is representative advanced packaging technologies that combine multiple integrated circuit dies into one package using silicon interposer. And 2.1D bridge technology, which inserts high-density circuit components into low-density boards, is also one of the advanced packaging technologies replacing 2.5D packaging. In common, both are based on the semiconductor technology of silicon wafer. PCB substrate makers have accumulated a variety of technologies for fine micro circuit. It is possible to prepare organic interposer replacing silicon interposer. A different approach has been tried to implement a 2.1D package substrate named eHDIL (embedded High Density Interconnection Layer) without silicon wafer and damascene process. Thin 4-layer organic substrate with L/S 2/2 was made by semi-additive process (SAP) on Cu foil with a removable glass carrier called HRDP. The thin substrate was implanted into a package substrate for 55um or less bump pitch chips such as HBM memory or chiplet through very accurate die mounting and via connection. Where the line pitch of the HDIL was 4 um, via diameter was 5 um, and total thickness was 30 um. This study demonstrates that advanced package substrates can be developed with PCB substrate material and technology.

The July 23rd webinar, “Electronic Essentials 101: What You Think You Know – and More,” presented by Greg Merrill, offered a practical refresher on core electronics concepts like voltage, current, resistance, and capacitance. Designed for both new and experienced professionals, the session revisited foundational principles while addressing common misconceptions and overlooked details. Through real-world examples, Greg highlighted how a deeper understanding of basic components can lead to smarter design decisions and fewer troubleshooting headaches. This session was ideal for anyone looking to sharpen their fundamentals and apply them more effectively in their work.

This article is a series of studies on a new generation of CPU socket challenges and component interconnect technology for high-end computer product applications. These products encompass computer server and data storage for cloud computing applications at the Data Center as well as core routers for service providers, edge, and branch routers for enterprise networking companies. All these cloud computing products require high data speed in Gigabytes per second and high signal integrity for the massive mobile users and IoT applications whenever and wherever the user wishes to connect. As the finer 3nm semiconductor process is progressively migrated into mass production in the chip fabrication industry to enhance transistor density, increase speed and lower the power consumption of the chip, there are great technical challenges in component packaging design with the circuit board.
The purpose of the Part 1 study is to look into the next generation of CPU socket design correlation with its interconnection system and PCBA manufacturability. Socket pin configuration related to pin true position and common bent pin issue due to transportation stress and material handling are very critical variables. Socket packaging design especially the cover will be carefully examined to avoid laser light leaking/reflection issue so as to avoid pick and place problems in device placement in the PCBA process. Past experience tells us the contamination at the contact pin interface such as particulate, process material residue and oxidation are very important variables to be controlled to avoid contact resistance issues. Socket material selection and mechanical construction are major contributors to package flatness and correlated warpage between the socket package and PCB.
The purpose of the Part 2 study is to look into the next generation of CPU socket design correlation with its interconnection system and PCBA manufacturability through a technical forum in the iNEMI (International Manufacturing Initiative) 2023 Board Assembly--CPU socket interconnect technology roadmap. A team of experts from CPU suppliers, socket material researchers, ODM companies initiated a review to brainstorm key technology trends for next ten years, to identify the technical needs, gaps, and challenges, and then propose potential solutions for the major technical issues. Over the next decade, there is a projected exponential increase in computer data rate in Gb/s due to the IoT from the massive mobile users in the field for their whenever and wherever needs. In such a trend, the socket pin count will be in exponential growth over time, mainly driven by the increase in total computer power, memory and input/output signaling bandwidth. With this exponential increase in pin count, there is a trend to push the similar increase in LGA socket mechanical loading. This increase in loading affects hardware complexity, costs and socket keep out area on the board which in turn could impact overall computation density per motherboard. The data rate increase overtime is forcing lower height sockets to meet the high speed signaling integrity requirement. This reduction in height can promote more complexity to the LGA pin design to meet mechanical requirements as well as forcing larger warpage in socket which can be an interconnect issue at the LGA and motherboard interface.

In modern manufacturing, the seamless coordination and efficient control of Surface Mount Technology (SMT) production lines rely significantly on strong communication and interoperability among heterogeneous equipment. This study employs a problem-oriented research methodology to delve into the intricate challenges stemming from non-standard communication protocols within SMT production lines. At the core of this investigation lies the pivotal role of the equipment connector—a linchpin for mediating communication across equipment from diverse vendors, each utilizing distinct protocols.
This research has two objectives: first, to comprehend and tackle the complexities posed by non-standard communication protocols within various equipment types present in SMT production lines; second, to illuminate the role of line controller in bundling individual equipment to operate as a single unit while seamlessly integrating with both upstream and downstream systems.
Through detailed case studies and analyses, we propose a standard communication platform with a centralized service to receive data from microservices, handle distinct protocols, and utilize Redis [1] as a cache for quicker data retrieval and messaging. This aims to tackle the complexities brought by heterogeneous equipment. The platform orchestrates equipment as chambers through segment segregation, transferring data between tools and cascading changeover. To better convey the equipment integration progression to users and vendors, we introduce a Rollout Checklist (RCL) that catalogs features and priorities.
In conclusion, this paper highlights line controllers as vital components to mitigate the challenges associated with diverse equipment sources. By offering a standardized communication platform, line controllers will enhance overall efficiency, adaptability, and performance in SMT production lines.

When the traditional server motherboard is designed in laminated structure, in order to ensure the symmetry of laminated structure, each layer is designed with the same material. With the upgrading of server products, the transmission rate of each signal layer is changing faster and faster, and better insertion loss of copper clad laminate(CCL) materials are needed to meet the signal transmission requirements, and the material upgrade brings about an increase in the cost of printed circuit board (PCB) materials. Through the PCB layout characteristics at each layer, it can be found that the length of the signal line at each layer is different. The longer the signal line, the higher the grade of material is required to reduce the overall loss. Lower grade materials are used in the layers of the shorter signal line, and higher grade materials are used in the layers of the longer signal line, and this material is asymmetrical laminated design to achieve lower material costs to meet the signal transmission requirements of all signal layers in the PCB. Due to different resin types, the expansion coefficient and shrinkage rate in different grades of materials will be different. The mixed pressure of the two materials will lead to the warping problem of the board due to the different shrinkage rate of the material, which brings great quality risks to the PCB manufacturing and printed circuit board assembly (PCBA) patch factory. The study of warping changes caused by mixed pressure of different laminates can provide more technical guidance for the lamination design of such products.

This paper first presents a summary of cycles-to-failures (CTFs) test data based on Weibull plots and failure analysis generated for small to large Quad Flat No-Lead (QFN) packages, which were assembled and subjected to standard thermal cycle/shock conditions for reliability evaluation. Then, it presents highly accelerated life test (HALT) results generated using the same QFN test vehicle configuration. The new HALT method was performed using test vehicle under vibration while holding temperature constant either at cold- (−20°C) or extreme cold-temperature (−100°C). The two QFN assemblies were subjected to 50g three-dimensional random vibration under the two cold temperatures. This test also fills existing gap on vibration as well as deep cold thermal cycle for high-reliability applications.
The two temperatures were chosen based on an analytical model that predicted the QFN solder joints at –20°C will be at the static elastic and at –100°C will be at the inelastic strain ranges. Only four representative daisy-chain QFN parts were monitored during HALT testing, but all daisy-chain resistances were verified manually after test. In addition, failure analyses were performed by optical inspection, scanning electron microscopy (SEM), and cross-sectional microscopy to determine failure mechanisms. The paper presents a brief discussion on analytical stress results, it provides detailed testing procedures and results, and optical/SEM images from failure analyses with discussion and findings.
KEY WORDS: HALT, accelerated life test, QFN, quad flat no lead, bottom termination component, BTC, MLF, thermal cycle, thermal shock, vibration, tin-lead solder, solder joint reliability.

Optical fiber array can realize multi-channel optical signal transmission. In the process of embedded PCB, the difficulty lies in laminating. The structure of the optical fiber array determines the need to design corresponding laminated structures and laminating parameters to ensure the integrity and reliability of the embedded optical fiber array. In this paper, the special laminated structure design, slotting design, and processing flow parameter settings are used to achieve the complete embedding of optical fiber array in PCB, and ensure that the product has good thermal reliability.