Assemblers of printed circuit boards seek to provide their customers with high-quality products at the lowest possible cost. The total cost of production must take into account the complete product lifecycle including warranty,recalls and repairs. Systems designed to achieve optimal use of materials and resources through the cleaning process can provide process engineers valuable information for reducing part to part variation and improved quality. Industry 4.0 tracking,monitoring and data analytics systems applied to the cleaning process can give process engineers real-time process information and quality data. An external data acquisition system utilizing analog-to-digital,digital I/O,encoder interface and barcode reading capabilities gives process engineers data on each board processed through the cleaning syst e m. Reflow conditions,wash chemistry control,temperature probes,pressure transducers,pressure switches,DI water resistivity and encoders can be integrated to monitor,track and accumulate data for real-time analytics. Applying analytics to the cleaning process improve quality and consistency lot to lot. Analytics gives process engineers the ability to gain insight from process data monitored and tracked while cleaning production assemblies. They allow engineers to identify common threads and valuable intelligence about system operations. Traceability of cleaning process conditions is a sure proof of compliance. This designed experiment monitors reflow and cleaning process conditions over an extended period. Data analytics will be applied to data from production PCB cleaning operations. Process issues discovered and proactive actions to keep the system in control will be reported.

In case of broadband technology,component packages and other devices assembled on the PCBs are ever-shrinking,yet demands for quality,precision and reliability remain the same. Thus,how can manufacturers ensure they are sufficiently clean to meet the stringent quality and reliability demands? It has been well documented that flux residues can lead to failure mechanisms such as leakage current,electrochemical migration and dendritic growth and these can negatively impact the reliability of the PCBs. This is especially true in the case of Class 3 assemblies wherein failure is not an option. Recent evidence has shown that it is becoming extremely challenging to consistently deliver the correct amount of solder using the screen printing process. More and more manufacturers in today’s production environment are overcoming this challenge by incorporating jet printing as an additional add-on step to add extra solder paste volume to solve such challenges. Solder paste jetting offers the flexibility to deposit the right amount of solder paste volume on the boards that have both miniature and large size components that need to be soldered adjacent to each other. Typically,jet printing pastes use Type 5 and 6 solder powder compared to Type 3 and 4 usually seen in screen printing processes. This poses several cleaning challenges. First,the presence of oxide for a given solder volume increases exponentially as solder powder becomes finer. Second,jetting pastes typically have a higher flux percentage than printed paste for the same volume and finally,the flux volume decreases in proportion to the pad size and the work load of flux increases for finer pitch applications. Recent findings have shown that solder pastes with reduced metal content and finer powder soldered via jet printing process (Type 5 and 6) results in cleaning challenges as compared to pastes soldered via stencil printing process (Type 3 and 4). Cleaning process settings that produced acceptable results for Type 3 and 4 pastes may produce insufficient results for Type 5 and 6 pastes. Anecdotal evidence with current industry companies indicates that as solder powder becomes finer,the resulting flux residues become more difficult to remove. This paper is part of an initial study executed specifically on jet printing (Type 5) solder pastes using multiple cleaning agents in both spray-in-air inline and batch cleaning systems. The results are further validated by several industry case studies.

Conventional Electroless Nickel/Immersion Gold (ENIG) currently available in the market is prone to black-pad defects (hyper-corrosion related failures) associated with de-wetting of solder. ENIG also suffers from brittle solder joint failures. Due to these reasons,there are field failures and reliability concerns of electronic assemblies -component disconnection which lead to overall malfunction of electronic assemblies. Moreover,most ENIG manufacturers/suppliers provide cyanide-based gold chemistry which has health and ecological hazards. The novel ENIG eliminates black pad-corrosion related issues,achieves robust solder joints and provides improved quality and reliability of electronic assembly. Also,it uses cyanide-free chemistry for the immersion gold process making it eco-friendly. This allows manufacturers to consume eco-friendly product while avoiding major field failures and resulting consequences. The root cause of black-pad defects has been identified as hyper corrosion activity at the gold and nickel-phosphorous interface which involves nickel depletion and an enrichment of phosphorous in localized areas. An interfacial engineering approach had been used to successfully eliminate black pad by achieving marked improvement in corrosion resistance. Corrosion tests have been conducted using the potentiodynamic polarization method and tafel plots were generated between novel ENIG and conventional ENIG. The results show 10x improvement in corrosion resistance. This has also led to improved intermetallics at the solder joint leading to robust solder joints and elimination of brittle failures. Ball Shear and Ball Pull Tests (Industry Standard based testing: JEDEC Standard: (JESD22-B115 &JESD22-B117) were conducted on novel ENIG based solder joints and conventional ENIG based solder joints. No solder joints (intermetallics) failures were found with the novel ENIG compared to 80% of failures found at the solder joints with conventional ENIG. Also,the force to induce failure increased by more than about 48% with the novel ENIG compared to conventional ENIG. A novel ENIG is eco-friendly and cost-effective with high corrosion resistance and robust solder joints for better reliability of electronic assemblies.

Solder joint reliability has been a key issue for electronic assemblies and microelectronic packaging for many years. Many different factors can affect the solder joint reliability,such as package construction,mechanical properties of solder joints,external mechanical and thermal stresses,and environmental change. In applications of portable electrical devices,the mechanical impact such as shock,bending and twisting plays an important role in the product’s reliability. When an electronic assembly experiences repeatable mechanical stresses,failure of the solder joint may be induced. In this study,we carried out a series of experiments to understand the failure mode of Sn-Cu solder joints under mechanical bending at the product level. By comparing two different designs with button/switches,the bending induced strain was found to be the key factor that makes the solder joint fail. Low strain-rate cyclic button push tests were performed with PCB board strain measured simultaneously by strain gage. A number of analytical methods were used to study the failure modes under different button push conditions,such as dye and pry,cross section,and X-ray. The black pad defect was observed with the Electroless Nickel Immersion Gold (ENIG) surface finish between the component and board pad,which contributed to the brittle fracture in the intermetallic region. Ductile fractures were observed inside the bulk solder,which was attributed to the high strain at low strain-rate cyclic loading during operations. To eliminate the solder joint crack and improve the interconnection reliability,alternative surface finishes and methods to reduce the board strain were suggested.

Storage time allowed between bare printed circuit board manufacturing and assembly is quite limited. Based on an interpretation of IPC standards,shelf-life of the surface finish is the limiting factor. A lot of boards are scrapped worldwide because they have exceeded their shelf-life. Size of manufacturing lots is limited due to the risk of overpassing shelf-life of stored PCB1. A three-year study involving PCB manufacturers,EMS2and OEMs3has been conducted to evaluate the possibility to extend the shelf-life. Details of the study will be described in this paper. More than five thousand samples with different finishes coming from different PCB suppliers have been aged in normal and accelerated conditions with or without additional packaging (none,anticorrosion paper,dry pack). Following ageing,solder ability has been evaluated by two methods. Solder spread test have been realized by an EMS involved in automotive market on its production line. Wetting balance test have been realized by an independent laboratory. Results summarized in this paper clearly indicate that actual limitations are very conservative,and that shelf-life in normal ambient conditions can beat least doubled,whatever the packaging conditions. New recommendations for storage conditions and limitation will be issued from this study. They will contribute to significant improvement of the worldwide electronic industry efficiency and costs.

Effective Roughness Dielectric (ERD) is a homogeneous lossy dielectric layer of certain thickness with effective (averaged) dielectric parameters. The ERD layer is used to model copper foil roughness in printed circuit board (PCB) interconnects by being placed on a smooth conductor surface to substitute an inhomogeneous transition layer between a conductor and laminate substrate dielectric. This work derives the ERD parameters based on the understanding that there is a gradual variation of concentration of metallic inclusions in the transition layer between the dielectric and foil. The gradual variation can be structured as thin layers that are obtained using the equivalent capacitance approach. The concentration profile is extracted from scanning electron microscopy (SEM) or high-resolution optical microscopy. As the concentration of metallic particles increases along the axis normal to the laminate dielectric and foil boundary,two regions can be discerned: an insulating (pre-percolation) region and a conducting (percolation)region. The rates of increase in effective loss (or corresponding conductivity) in these two regions differ significantly. The proposed model of equivalent capacitance with gradient dielectric is applied to STD,VLP,and HVLP foils. The frequency-dependent dielectric parameters of the homogenized ERD are calculated from the equivalent capacitance. The results are validated using 3D numerical electromagnetic simulations. There are two types of numerical models: with homogeneous ERD parameters,as well as layered. Both models show excellent agreement with measurements.

Imbalanced weakly and strongly edge-coupled differential pairs on printed circuit boards (PCBs),both microstrip (MS) and stripline (SL),are studied under different conditions using mixed-mode S-parameters. The r ate of coupling between the lines influences both signal integrity (SI) and electromagnetic compatibility (EMC) of the PCB design. Weakly coupled lines are preferable for SI,but this is not always the case for EMI. Common-mode and mode conversion that negatively affect EMC are typically higher in the weakly coupled cases than in the corresponding strongly-coupled. This is due to technological factors such as the difference in lengths of lines in a differential pair; trapezoid cross-section of signal traces; copper foil roughness; solder mask over microstrip lines; and presence of an epoxy-resin pocket between the stripline traces. In this work,results of 3D full-wave numerical electromagnetic modeling,taking into account these various technological features,are compared with the measured results on the designed test fixtures.

It is common for PCBs used for high frequency RF or high speed digital applications,to be tested for an impedance value prior to shipping the board. The controlled impedance board is typically specified to a nominal impedance value with a given tolerance. Some time ago a tolerance of ± 10% was considered acceptable however recently and with more demanding applications,the impedance tolerance is often much narrower. Understanding the many aspects of impedance is beneficial to the PCB fabricator and designer,who are often required to make a judgment for product shipment based on the impedance measurement. There are several different types of impedance however characteristic impedance is normally specified for a controlled impedance PCB. This circuit property has many variables and some variables are related to the PCB manufacturing process,some are associated with material properties and some variables are due to measurement techniques. Additionally,some of these variables are more or less dominate for a particular type of circuit design and / or construction. This paper will give an overview of the basic theory for impedance,with an emphasis on characteristic impedance for circuits of different design types. Microstrip,grounded coplanar waveguide (GCPW) and stripline structures will be discussed with their unique impedance attributes. PCB fabrication related variables,as well as material variables,will be illustrated using modeling software and verified with measured results. The variables associated with impedance measurement are many and details will be given for several related issues. One variable,often not recognized,is masking and that is how the impedance value of a circuit can be altered due to an impedance spike which is located prior to the body of the circuit. Masking can cause inaccuracies for impedance measurements and there are ways to minimize this concern,which will be illustrated. The impact on impedance resolution and accuracy due to rise time will also be demonstrated with measured examples.

A novel lead-free solder alloy 90.6Sn3.2Ag0.7Cu5.5Sb (SACSb),was developed targeted for high reliability with a wide service temperature capability. The alloy exhibited a melting temperature range of 223 to 232?C,reflowable at profile with peak temperature 245?C and 255?C,with ambient temperature Yield Stress 60MPa,UTS 77 MPa,and ductility 28%,and a higher stress than both SAC305 and 90.9Sn3.8Ag0.7Cu3Bi1.45Sb0.15Ni (SACBSbN),the latter two alloys were used as controls. When tested at 140?C and 165?C,the die shear stress of SACSb was comparable with SACBSbN but higher than SAC305,and the ductility was higher than both SACBSbN and SAC305,with SACBSbN exhibiting distinct brittle behavior. When aged at 125?C and 175?C,the die shear strength of SACSb was comparable or higher than both controls. When pretreated with a harsh condition,a temperature-shock test (-55?C/155?C) for 3000 cycles,the die shear strength of SACSb was 8 times of that of SACBSbN and SAC305. When pre-conditioned using a temperature-cycling test (-40?C/175?C) for 3000 cycles,the die shear strength of SACSb was 11 to 20 times higher than that of SACBSbN and SAC305,depending on the flux type used. Both SACSb and SACBSbN are alloys based on SnAgCu,but reinforced with precipitate hardening and solution hardening,with the use of additives including Sb,Ni,and Bi. SACSb exhibited a finer microstructure with less particles dispersed,while SACBSbN exhibited more particles with some blocky Ag3Sn plates or rods. SACSb is rigid and ductile,while SACBSbN is rigid but brittle. Under the harsh test condition where ?T was high,the dimension mismatch between parts and substrate became very significant due to CTE mismatch. This significant dimension mismatch would cause a brittle joint to crack quickly,as seen on SACBSbN. The challenge was more tolerable for a ductile joint,as shown by SACSb. Accordingly SACSb showed a much better reliability than SACBSbN under harsh conditions,including high testing temperature and large ?T. Overall,to achieve high reliability under a wide service temperature environment,a balanced ductility and rigidity for solder alloy is critical for success.

Electronics manufacturers are searching for new lead-free solders that can improve upon SAC305 voiding performance and that exceed the current thermal cycle performance of this solder in harsh environments,all the while being processed at or near current typical SAC305 peak temperatures. This paper compares -40ºC to 125ºC,thermal cycle test (TCT) results of boards built with SAC305 and a newSAC347+Bi/Sb/Ni/Co solder paste,which were assembled to intentionally contain three levels of voiding,ranging from 0%to 0.5%,5% to 20% and higher than 20%,in order to not only observe variation in TCT performance but find any correlation between voiding levels of up to 30% and the corresponding thermal cycle reliability of the solder joint.