Creep corrosion on printed circuit boards (PCBs) is the corrosion of copper metallization and the creeping of the copper corrosion products across the PCB surfaces to the extent that they may electrically short circuit neighboring features on the PCBs. The paper will report the results of a round robin evaluation of the modified iNEMI creep corrosion qualification test. The earlier versions of the test involved testing in a specially designed flower of sulfur (FoS) chamber for 10 days at nominally 81% humidity level provided by KCl saturated salt solution. The modification to the iNEMI test was the change to three 5-day test runs,the first 5 days at 31% relative humidity provided by MgCl2saturated salt solution,the 2nd5 days at 47% relative humidity provided by NH4NO3saturated salt solution and the 3rd5 days at 81% relative humidity provided by KCl saturated salt solution. The rest of the test procedure remained unchanged,with the iNEMI designed setup providing somewhat controlled and reproducible concentration of chlorine gas and a tray of sulfur for providing sulfur vapors. As usual the test was run at a constant 50oC. The paper will compare the round robin test results from three companies on immersion silver (ImAg),electroless nickel immersion gold (ENIG) and organic solderability preservative (OSP) finished PCBs soldered using organic acid (OR) and rosin (RO) fluxes. As expected,the ENIG finished PCBs suffered the most creep corrosion while the OSP finished PCBs suffered the least creep corrosion. The paper will also list the copper and silver corrosion rates experienced during the test runs and discuss means of better control of these corrosion rates.

The European Union RoHS directive took effect in 2006,and of the 6 restricted materials,the elimination of lead from electronic devices took the most development effort and had the worst degrading effect on hardware reliability. One negative impact was the brittleness of the lead-free solder alloys that replaced the industry favorite,ductile Sn-Pb eutectic alloy. Another was the unexpected occurrence of creep corrosion on printed circuit boards using alternative PCB surface finishes. Along with the implementation of RoHS,the miniaturization of circuits,the expansion of IT markets in developing countries with high-levels of sulfur-bearing gaseous pollution,and the trend towards energy saving by resorting to free-air cooling,have all led to increased rates of corrosion-related hardware failures associated with particulate and gaseous contamination. The IT industry has taken a two-pronged approach to mitigating these failures: (1) by making the products more robust against contamination and high humidity levels; and (2) by gaining better understanding of the allowable levels of contamination,temperature and humidity under which IT equipment can operate reliably. Additionally,many points along the supply chain have been identified where corrosion can form,and the additive effects may or may not be detected by testing or manifest themselves before delivery to the end-user. Failures at this point may be due to the cumulative effect of numerous “micro-failures” generated throughout the supply chain. However,what remains most frequent are product failures resulting from exposure to elevated pollutant levels and inadequate environmental controls at manufacturing locations. The result is an operating environment that does not meet current manufacturers’ warranty requirements – requirements that have been put into place since the implementation of RoHS. This paper will describe the common modes of corrosion-related hardware failures in the past 10 years,the actions taken to make the products more robust,the understanding of the role played by contamination,and the means of negating their detrimental effects. The case will also be presented for environmental monitoring at various points along the supply chain and the addition of enhanced air cleaning for those locations that do not meet the air quality requirements of the finished devices. Data will be presented that highlight the need for air quality assessments of manufacturing facilities,where enhanced air cleaning is indicated,and the benefit of establishing an ongoing real-time air monitoring program to assure compliance with air quality specifications and warranty requirements.

Over the past few years,studies have shown that Nano-coatings can improve solder paste release and reduce underside cleaning in the print process. Many of these studies have focused on print volume and the improvement of transfer efficiency in small component printing. This paper investigates whether Nano-coated stencils improve repeatability and uniformity in the print process for a range of components sizes. Repeatability and uniformity were defined as how tightly controlled print deposits were from print to print over time. Solder paste inspection (SPI) data was collected and analyzed for the following component types: 01005 up to 1206 Imperial chip components; 0.5mm pitch micro BGA components; 0.4mm pitch up to 1.25mm pitch QFP components and 0.4mm pitch up to 0.6mm pitch QFN components.

The mobile and consumer market is the driving force of the electronics assembly sector,this sector historically has been associated with early adopters of leading edge surface mount technology (SMT). The main driver for adopting state of art SMT is the consumers demand for greater user functionality. Meeting this demand requires integrating more into less,or to give its correct term –Miniaturization. The assembly community has become used to the introduction of new smaller feature sized devices. The next device that will drive this next round of miniaturization is the Metric 0201(M0201). This passive device will measure 250um x 125um and offer a 60% reduction in real-estate to its predecessor. The M0201 will be used in both Systems in Package (S.I.P) and consumer electronic applications. The implementation of the M0201 within the S.I.P application will result in a homogeneous solder paste solution,as a consequence the stencil thickness can be chosen to ensure aperture area ratios are well within the IPC recommendations. However,the implementation of the M0201 device within the mobile and consumer sector will result in a heterogeneous solder paste solution. Within this heterogeneous environment the stencil thickness will be comprised due to the volumetric requirements presented by the mixed technology application. The combination of sub 150um apertures and standard stencil thickness will lead to area ratios falling below the IPC recommendations. Previous research into printing challenging area ratios has focused on an improved method of filling the apertures through the utilization of ultrasonic squeegees and novel stencil coatings. Although the filling process is a major element to the printing process,the release of the aperture is equally as important to delivering a repeatable solder paste deposit. From a release point of view,an aperture is the structure that forms and molds the solder paste deposit. It is also from this aperture that the deposit has to release from. The incumbent aperture design for passive chip devices has been a regular polygon (rectangle) design,one that traces the outline of the device land. Within this study the inclusion of a radius within rectangular aperture geometries will be investigated. The influence of a radius will be measured against the resultant volumetric Cp/Cpk values. The study will include three aperture designs that are compatible with the next generation devices,each aperture design will include six radii profiles. The findings from this investigation will show if any process improvements can be associated with the inclusion of a radius within a regular rectangular aperture design.

Most manufacturers of electronics grade glass fiber reinforcement used in today’s laminates apply treatments to enhance the bonding strength between the inorganic e-glass and the epoxy matrix which surrounds it in the laminate structure. These treatments,when properly formulated and applied on the glass fibers help to prevent glass-resin delamination due to mechanical stresses or due to thermal excursions during the laminate lifecycle. The thermal excursions can include multiple reflow cycles followed by wave soldering and in some common circumstances a cycle or two of rework. However,such laminates continue to develop glass-resin delamination that promotes a form of electro-chemical migration that leads to a loss of electrical insulation resistance between opposing biased conductors. This phenomenon is commonly known as conductive anodic filament (CAF). The glass-resin delamination can also contribute to a reduction in the mechanical flexural strength,which is not the focus of the present paper. The probability of CAF failure is a function of temperature,moisture content,the voltage bias,manufacturing quality and processes,materials and other environmental conditions and physical factors. The present paper discusses the glass treatments and examines the effects of thermal and combined thermal/moisture exposure on the glass-resin interface. Atomic force microscopy is used for examination of sites to track the state of degradation and changes in the mechanical properties. Micro-Fourier transform infrared spectroscopy is used to track the progression and diffusion of the inter-penetrating network formed as a result of inter-diffusion between the glass-treatments and epoxy laminate material. The results of the studies are expected to show the progression of damage and provide unique quality assurance and failure analysis insights into this less reported contributor to printed circuit board quality.

Internet of Things (IoT) adoption pushes the boundaries of Printed Circuit Board (PCB) miniaturization and speed employing more hybrid stack-ups. The complexity of PCB stack up designs,material selection,advanced processing,and subsequent assembly requirements are driving novel approaches to accelerate engineered solutions. To support the aggressive PCB product development cycle times,the accuracy of physics-based predictive modeling must improve,and the number of lengthy Design of Experiments (DoE) minimized. To facilitate this,effective material characterization techniques and modeling capabilities of these complex systems have been developed,with the goal to mitigate risk,increase reliability and reduce engineering time while ensuring a manufacturable solution. In general,the stress induced on interconnects increases as the interconnect size decreases. However,to accurately model the physical behavior (stress and strain) of PCB interconnects in design stack ups during a reflow or lamination processes requires material property information which necessarily is not present on a typical materials’ supplier datasheet. Some parameters are also not readily available using standard measurement techniques. Additionally,typical numbers in a laminate datasheet only apply to a standard glass style and resin content. Glass style and resin content have a dramatic influence on the end product mechanical properties. Also,the composite nature of PCBs not only result in its thermomechanical behavior to differ along the X,Y,and Z directions,but also relax over time due to the viscoelastic nature of the epoxy resin. Therefore,the anisotropic and viscoelastic properties of PCB materials must be measured. The measurement techniques discussed here are not part of any formal IPC testing protocol currently. However,they capture properties of PCB materials at the small scale very effectively. They rely on using a Dynamic Mechanical Analyzer (DMA)instrument for measurement purposes. These advancements in material characterization and modeling provide insights into micro-via reliability for next generation PCB miniaturization and high-speed signals.

Printed wiring boards(PWBs) have recently been experiencing higher thermal stress in car electronics and high current equipment,etc. In this study, the effects of structural factors and material properties on thermal fatigue life of plated through hole (PTH) in multilayer PWB havebeen investigated by finite element method (FEM) based on Box-Behnken experimental design.This methodology showed the effects of single factor and interactions of multiple factors of PWB on the strain causing an occurrence of cracks in copper (Cu) plating of PTH. The simulation was conducted with obtained properties of thin Cu plating in previous research and a model of a simplified glass cloth equivalent to a cross section of a PWB. It became clear that the effects of Cu plating thickness of PTH,CTE (coefficient of thermal expansion) and elastic modulus of PWB material were significant on inelastic strain range (?ein) in PTH during thermal fatigue. PTH pitch,though,did not haveameasurable impact. The influence of PWB material Tg was found to be so overwhelmingly strong in the experimental design that behavioursof other factors became too muted to be analysed,which means Tmax should be below Tg. A formula of the ?ein,in consideration of the significant factors and its temperature-scaling factor related to ?T,was proposed.In addition,the ?einbecame large in accordance with shape and size of roughness of PTH. When the Cu plating of PTH obeys Manson-Coffin rule, the thermal fatigue life of PTH in consideration of the structural and material factors,can be predicted by the proposed formula on?einand the low-cycle fatigue life prediction law of Cu plating obtained by previous research. Theacceleration factor(AF)equation was established and validated by test data using various PWBs and temperature conditions in temperature cycling test (TCT). The calculated AF roughly agreed with the ratios of Weibull average of TCT results.

This work presents the fabrication of embedded inductors and the experimental laser machining of gaps in the underlying ferrite structure. Design calculations are presented for a test coupon of power inductors. These devices are designed for use in DC/DC converters operating in the 500kHzto 5 MHz range and having inductance values between 1 to 10 uH. The power inductors are constructed by embedding on a ring-shaped ferrite cores (toroids) into an FR-4 substrate,laminating copper foil to the top and bottom surfaces,imaging and etching conductive windings on the top and bottom surfaces. The windings are interconnected with plated-through-hole (PTH) vias. Gapping can be achieved with different laser systems,each having specific benefits and trade-offs. For this experiment,a YAG laser system was used to produce a 0.2 mm gap into a 6.35 mm OD core. Inductance values are presented for before and after the gapping procedure.

As the IoT market demands higher data rates and processing,the PCB technology is driving for smaller form factors,higher signal densities,and advanced material solutions. Miniaturization has been a common trend. Besides reduction in transmission-line and space widths,higher density and bump pitches down to 200 microns,as well as smaller diameter microvias down to 50 microns will be required. The finer features challenge suppliers of equipment,chemistry and materials to find solutions to support the PCB fabrication requirements. This presentation addresses the science and technologies developed in collaboration with supply partners to understand,develop and deliver a 10-layer“substrate-like PCB+” (SLP+) with50 micron diameter stacked microvias,transmission line and space of sub-25 microns and full array 200 micron pad pitch circuit technology solution to enable the next generation of IoT PCB requirements. This SLP+ technology goes beyond the MSAP/SLP technology that several suppliers are currently implementing. The sub-25 µm line and space is achieved with a modified semi-additive process (MSAP) that electroplates copper through openings in the dry-film,instead of using the dry-film as an etch resist. The initial SLP+ designs with leading smartphone customers and M2M modules are in the development phase. The extension of this technology drives feature sizes down to sub-25 micron line/space and 200 micron solder-bump pitch and below. This technology allows down to 200 µm pitch ICs to be directly attached to the PCB,thereby eliminating the need for a BGA substrate. Without the BGA substrate,reductions in z-height are achieved. The thermal resistance to the PCB plane and any rear heatsink is reduced by eliminating the BGA substrate. Similarly,signal integrity is improved by removing impedance discontinuities at the additional interfaces of the BGA substrate. Consumers will see their devices shrink beyond the current state-of-the art,and with performance improvements. The presentation will demonstrate ‘advanced high-density interconnect’ produced in high volume in collaboration with suppliers. The interconnect solutions include a single line between pads at 200 µm-pitch,and two lines between pads at 250 µm-pitch. Thermal cycling (air-to-air and liquid-to-liquid),and 10X solder reflow reliability test results will be presented.

Misregistration of holes is the maximum amount of variation between the centerlines of all terminal pads within one plated through hole in a printed circuit board. The impacts of misregistration can be very serious due to possible electrical opens caused by breakouts or a short or intermittent connection due to a violation of the minimum clearance. This study highlights the differences in registration in Printed Circuit Board (PCB)samples made by the same supplier at two geographical locations. The intent is to determine a statistical correlation between the populations of registration error measurements taken on samples,from layer-to-layer or across layers,and reliability or performance risk. The study includes comparisons between PCB samples made in both the locations. The focus of the comparison includes studying whether both populations reflect the same statistical results,trying to understand where the difference in population occurred and maybe answer the question -which population has the lower amounts of misregistration between layers. Misregistration occurs during board fabrication and is directly attributed to problems involved with the production of the artwork,with artwork materials,with the setup procedures during lamination,and/or with the dimensional instability of the laminate materials used.