The following article is a series of “from the trenches” stories,taken both from the perspective of an electronics manufacturer and an environmental compliance consultancy. The accounts below provide a library of RoHS compliance scenarios that illustrate the extremes of building an RoHS compliant product and the pitfalls of assuming that a declaration of compliance is iron-clad.
Unlike most papers,portions of this one are written in first person. In order to preserve both the confidentiality of our sources and the integrity of this paper,all external stories provided to us have been copied into the paper and kept anonymous. This allows for a non-biased and often humorous accounting of RoHS.

Embedded passives,especially embedded resistors and capacitors have been a hot topic since the mid-to-late 1990s. It is easy to understand why they have generated so much interest. Technology continues to be driven by performance,space and cost. Embedded passives offer potential significant advantages in each of these areas.
Embedded passives have far less parasitic inductance than discrete components,which enables electrical performance advantages (noise and EMI reduction),especially in high speed digital applications. Embedding passives saves surface real estate,which allows for board size reductions which is critical in space constrained designs such as military/aerospace and portable products. The incremental cost of embedding additional passive components is typically negligible; this offers the potential for system cost reduction in designs with high passive component counts. Embedded passives also offer additional advantages such as improved reliability and weight reduction due to the elimination of vias and solder joints.
However,even with all of their potential advantages,high performance embedded passive materials remained a niche market
until the last couple of years. There were a number of reasons for this,including the typical fear of new technology,limited technical resources and funding,lack of successful case studies,lack of an experienced supply chain,lack of long term reliability data,very limited physical layout and simulation/modeling software tools,improvements in existing discrete passive products,the telecom bust,cost concerns and an insufficient knowledge of intellectual property and prior art.
After more than 10 years of large scale interest,high performance embedded resistors and capacitors have finally become mainstream technologies in many market segments. There are multiple suppliers of commercial thin film metal resistor materials and ultra thin embedded capacitor materials. A large number of PCB fabs across the globe have very significant experience in processing these materials in moderate to high volumes.
This paper will look at the above barriers to the implementation of high performance embedded passives,focusing on embedded capacitor laminate materials,and show how these barriers were overcome so that embedded passives could finally become a mainstream technology.

There are presently several techniques for forming a buried capacitor in the core of a multilayer board. For purposes of this discussion,attention will be directed toward a sheet capacitor; although most of what is presented below can be extended to the other techniques as well. A buried sheet capacitor is essentially a thin innerlayer. The core is composed of an organic material often reinforced with a woven glass structure. A classic example is FR-4. The laminate extends over the entire board and is essentially a very thin innerlayer. The copper weight is normally one ounce and the thickness of the dielectric is typically two mils or less. The innerlayer is biased top to bottom thus creating a large capacitor in the interior of the multilayer board. Except for through hole connecting pads and antipads the innerlay is normally not imaged. A cross-section is depicted below:
The purpose of this technology is to offer the designer a technique for EMI suppression and an alternative to the by-pass capacitors normally mounted on the surface of the board to minimize “voltage sag” in the power being supplied to the active devices. A more complete discussion of the electrical performance will follow later.

A new technology for MLB pressing has been developed by MBT and industry partners,called TOP,Temperature Optimised Process. The goal was to reduce energy consumption and to improve product quality by quicker and more even heat distribution throughout the book. This was achieved by using new materials and direct electrical heating of the tools. Tools are made using a 3- ply-material having a core of Aluminium and both sides clad with Stainless Steel. This gives 90% of the heat conductivity of Al combined with the thermal expansion and surface hardness of rolled Stainless Steel. Each part of the tools is heated by a specially developed ultra thin heating element having a connection capacity of only 3 kW/h. Build in sensors allow each heating element to be controlled separately so that only the actually needed energy is supplied. Each opening can be controlled separately. A third heating element is placed in the middle of the book,thus actually creating 2 books in one allowing for up to 50 mm MLB material to be in each book / opening. All connections for energy and sensors
built into the tool have their matching parts in the back of the press to have direct contact when putting the tool inside the press. Depending on the structure of the panels it takes 30 – 45 minutes from cold start to reach 200° C in book centre. Another important part of TOP is our patented Separator HTS 600. Having a thickness of only 0.5 mm HTS 600 has about 4 times better heat conductivity compared to Stainless Steel. Due to quick and even heat distribution no press pads are needed. Very tight thickness tolerances are achieved by even resin flow. Cooling is done by water circulation inside the top and bottom tool either under full pressure or controlled cooling/pressure ratio. This gives unequalled stability and extremely low shrink in X and Y axis. All above has been established by test runs with a number of German Customers and assistance by ISOLA Düren.

As PCB designs become ever more complex with more sequential build up layers,tighter annular ring designs and broader range of advanced materials,understanding the effect of material distortion is critical to maintaining yields. Determining the inner layer scale factors to compensate for various material movements is also becoming increasingly difficult and with the additional constraints of the “quick turn” market there is no longer the luxury of running scale factor test batches – the first batch made must be delivered to the customer.
Latest generation drilling and imaging equipment provides the ability to automatically scale the drill program or image to match each panel manufactured. These capabilities ensure accurate registration of the relevant processes,but if scale errors have already been made on the inner layers,these errors are being followed throughout the manufacturing process and will ultimately be delivered to the end customer. To provide products of nominal dimensions to the customer,the original inner layer scale factors must be accurate and an intelligent compensation system should be used at these processes to reduce or eliminate the effect of variations upon the product received by the customer.
This paper analyses the data from a variety of product designs and constructions made at numerous facilities worldwide and demonstrates the influence of this variety upon the required scale factors. By comparing production results over two years and additional experimentation by the author,this papers shows that the variations exhibited can not be accounted for by simple look up tables and a more complex model is required to accurately predict the correct scale factors for new product designs. The paper will also outline the concept of an intelligent compensation system and how this could be applied to the manufacturing processes.

This paper discusses a new technology to improve etching performance using shiny side surface treatment on copper foil. Until now,a lot of electro-deposited copper foils (ED foil) with very low profile on matte side have been introduced to the market to obtain fine line products such as HDI. In addition to copper foil thickness,roughness of matte side is thought to be a key factor to improve etching performance. However,our new technology is quite unique and different from other methods to obtain narrow traces. Using new technology,30 micron pitch circuits could be obtained using 9 micron copper foil.

The purpose of this study is to investigate the optimum plasma processing as a pre-treatment for the surface of Polyimide (PI) in order to increase adhesion strength of electroless copper (Cu) plating to PI directly. Two kinds of oxygen (O2) plasma processing were applied and compared in the experiment to investigate the optimum plasma processing. One method was surface wave plasma (SWP) processing generated by the microwave plasma reactor with the 2450MHz microwave power source. The other processing method was reactive ion etching processing generated by the capacitively coupled plasma reactor with the 13.56MHz radio frequency (RF) power source. The processing characteristic of microwave plasma which has comparatively higher electron density than that of RF plasma is anisotropic chemical etching processing without collision of electrically-accelerated atoms to processing objects. On the other hand,the processing feature of RF plasma is isotropic processing with ion bombardment and reactive etching to processing objects. The first part of this paper described the result of the surfaces roughness formed by two types of plasma processing under various processing time. The surface roughness was evaluated by atomic force microscope (AFM) measurement. The AFM measurement showed that the surface roughness formed by the SWP processing was much smaller than the surface roughness formed by the RF plasma processing. In the second part of the paper,chemical conditions of the PI surface measured by X-ray photoelectron spectroscopy (XPS) were investigated after SWP and RF plasma treatments. The measurements of XPS showed that large number of hydroxyl groups as well as the functional groups -C=O were observed on the surface of PI treated by SWP. In the case of RF plasma treatment,hydroxyl as well as the functional groups -COO was observed on the surface of PI. The functional groups -C=O was not observed on the surface of PI treated by RF plasma. The final part of this paper focused on the relationship between peel strength of electroless Cu based on treated PI measured by T-peel test. T-Peel adhesion strength measurement proved that PI surface treated by the SWP processing was greatly improved in adhesion strength without forming surface roughness or seed layers. On the other hand,electroless Cu adhesion strength after the RF plasma treatment was comparatively weak due to forming the excess surface roughness of PI due to oxygen ion bombardment and isotropic reactive etching.

The advent of miniaturized electronics for mobile phones and other portable devices has required the assembly of smaller and smaller components. Currently 01005 passives and 0.3 mm CSPs are some of the components that must be assembled to enable these portable electronic devices. It is widely accepted that about 65% of all end of the line defects occur in the stencil printing process. Given all of the above,it is critical that a precision stencil printing process be developed to support miniaturized electronic assembly.
This paper is a summary of a significant amount of experimental data and process optimization techniques that were employed to establish a precision SMT printing process. Our results indicate that the industry standard stencil aperture area ratio requirement of > 0.66 is an excellent rule of thumb. However,by optimizing printer setup with vacuum support,foilless clamps,squeegee edge guards etc and assuring cleanliness and squeegee and stencil quality,we have been able to obtain acceptable stencil printing results with area ratios of 0.5 with Type III solder pastes. The work that was performed to achieve these results will be discussed in detail in the paper.

The Surface Mount Technology (SMT) industry has overcome many challenges in the last 30 years,since its introduction in the 1980’s. One recent challenge has been the lead-free assembly. People have been working for more than ten years to address this challenge. While the industry is finally getting a good handle on the lead-free assembly process,another significant challenge has begun to surface. The most current challenge is the adoption of miniature components assembly process. Miniature components used today includes 01005,0201 passives to 0.3 mm-0.4 mm CSP and BGA.
By itself,miniature components have their own challenges,but when combined with larger components on the same board,the challenges multiply by several fold. To make matters worse,the design and functionality demanded by consumers require the placement of miniature passives next to larger,castle-like components. This creates a fundamental challenge in satisfying the solder paste need for both small and large components. Even though this is an industry-wide issue,no significant studies can be found in the literature. There are many different approaches that can be taken to address this issue. These include step stencil,augmented stencil printing process,multiple printing passes,etc.
In a recent publication,Speedline reported work done at a very basic level to understand the printing challenges associated with “Broadband Printing”. Broadband Printing is defined here as the printing process that satisfies the solder paste volume required for a PCB with both miniature and larger components existing side by side.
This paper will investigate the capability of a single thickness stencil to satisfy the paste requirement for mixed components board by creative stencil design. Some of the stencil design factors that will be explored will include over printing of larger components,using different stencil technology,and stencil thickness. In addition to the printing study,components will be placed and reflowed to access the solder joint character. The post assembly boards will be inspected by using IPC-A-610 standard for fillet characterization. In addition,X-ray inspection and mechanical strength test will be conducted to characterize the solder joint integrity.

Some of the new handheld communication devices offer real challenges to the paste printing process. Normally,there are very small devices like 01005 chip components as well as 0.3 mm pitch uBGA along with other devices that require higher deposits of solder paste. Surface mount connectors or RF shields with coplanarity issues fall into this category. Aperture sizes for the small devices require a stencil thickness in the 50 to 75 um (2-3 mils) range for effective paste transfer whereas the RF shield and SMT connector would like at least 150 um (6 mils) paste height. Spacing is too small to use normal step stencils.
This paper will explore a different type of step stencil for this application; a “Two-Print Stencil Process” step stencil. Here is a brief description of a "Two-Print Stencil Process". A 50 to 75 um (2-3 mils) stencil is used to print solder paste for the 01005,0.3 mm pitch uBGA and other fine pitch components. While this paste is still wet a second in-line stencil printer is used to print all other components using a second thicker stencil. This second stencil has relief pockets on the contact side of the stencil any paste was printed with the first stencil.
Design guidelines for minimum keep-out distances between the relief step,the fine pitch apertures,and the RF Shields apertures as well relief pocket height clearance of the paste printed by the first print stencil will be provided.