The regulation requiring lead-free solders for printed circuit boards (PCBs) has presented a number of challenges to our industry at virtually every stage of the process. For the brominated epoxy resins used to make a large fraction of the laminates that serve as the starting material for PCBs,the requirement for higher thermal stability has led to increased use of phenolic curing agents in place of dicy. The good news is that brominated formulations are available that can be used to make laminates that meet the highest IPC specifications for glass transition temperature (Tg > 170 °C) and decomposition temperature (Td > 340 °C). However,phenolic curing agents lead to some compromises in other properties,especially toughness and copper adhesion. A general comparison of the properties of phenolic cure vs dicy cure will be made,along with some guidelines for application. The thermal stability of non-brominated resins is inherently greater than that of brominated resins,and meeting the highest Td specifications is not a challenge,even with dicy cure. Therefore non-brominated resins are well suited for lead free applications. Furthermore,unfilled non-brominated resins have improved dielectric properties and lower densities. However,non-halogenated resins are more expensive and exhibit greater water absorption. Achieving high Tg’s (> 170 °C) can be a challenge,but this is now possible with commercially available materials. A comparison between brominated and non-brominated resins will be made.

Silicones are often used to protect electronic applications designed for cold environments. The low temperature flexibility
of silicones is well recognized,but not as well understood. While the actual Tg of silicones is about -120°C,they do
transition from a soft rubber to a harder rubber around -45°C. At the transition their hardness,strength and modulus
increase slightly while elongation decreases slightly. Very soft silicone gels show the greatest change,becoming more
rubbery and in some cases showing tears. These tears can self-heal within a few weeks at warmer temperatures.
The specific temperature where these changes take place is shown to be dependant on the rate of cooling. Slow cooling
will show this transition around -45°C for many silicone elastomers. Analytical tests may indicate performance limits that
are too conservative. On the other hand,rapid cooling and short dwell times often used in thermal shock and cycling tests
may not detect stress changes that could occur in slower cooling conditions unless a sufficiently long low temperature soak
is included in the testing regime. Lower temperature versions of silicones are available that do not show property
transitions until -80°C or even until -120°C.

While glass fibers are commonly used to reinforce circuit board substrates,they have a high dielectric constant and loss.
Cyclic olefin copolymer fibers have a lower dielectric constant and loss. By combining these fibers with glass fibers in
unique hybrid cloths,we have made circuit board substrate materials with a dielectric constant of 3.08 and loss tangent of
0.013 using standard epoxy resins that are common in FR-4 glass reinforced substrates. The comparative glass materials had
a dielectric constant of 4.49 and loss of 0.019. In another embodiment,the cyclic olefin copolymer fibers were melted to
form the resin component,yielding a substrate with dielectric constant of 3.25 and loss tangent of 0.0013. In the last
example,a special low dielectric resin was used,giving a substrate with dielectric constant of 2.8 and loss tangent of 0.0009.
Substrates made from this fiber have passed Peel Strength,Solder Float,Water Uptake,and have a low coefficient of thermal
expansion.

(not available)

CTE mismatches during temperature cycling can cause significant movement of components and materials relative to one
another,which in turn stresses solder joints and wirebonds. Silicones are often used to protect electronic devices,and the
large CTE of silicones can be of particular concern,though the very low modulus of these materials tends to greatly mitigate
stress. While a few examples of potential damage caused by thermal expansion of silicones do exist,a level of understanding
of the magnitude of expansion pressures would be helpful in design,validation,and thermal reliability testing.
A study was begun to measure the pressures developed during thermal expansion of typical silicone encapsulants used in
electronic applications. A range of products was evaluated to encompass very soft gels to medium hard elastomers. Harder
elastomers were found to generate 0.2 psi/degree C rise in temperature,while soft gels generated <0.01 psi/C and extremely
soft gels <0.001 psi/C. Application variables such as part design geometry are discussed and shown to potentially multiply or
concentrate the generated pressures. Validation of experimental results was made with a case study.

(not available)

As electronic packages keep shrinking in size,high-speed high-accuracy package assembly equipment are becoming more
sensitive to mechanical vibrations. Alignment,positional and pick & place accuracy can be compromised during high speed
operation due to sensitivity to mechanical vibrations which are generated within the assembly equipment,as well as from the
floor and neighboring machines. Vibrations can also affect process yield as a result of diminished accuracy. Semiconductor
package manufacturers are under constant pressure to increase output,at the same time are challenged by tighter alignment
accuracy requirements.
This paper describes the methodology used to characterize the vibration response of manufacturing equipment under
vibrating floor environment,and that of the manufacturing floor under vibration induced by operational equipment. Case
study of pick & place equipment shows significant differences in vibration levels were found in different building facilities
and factory floor conditions. Also described in the paper is reason why a standard/specification is needed for purchased
assembly equipment. Industry standard needs to be developed that can help specify how much vibration can be transmitted
from the machine to the floor,and how much internal and external vibration the machine should be able to withstand without
affecting performance or quality and reliability. Examples of possible solutions that manufacturers and equipment suppliers
can adopt to meet future needs for precision high-speed placement equipment are also discussed.

Due to the ever-aggressive
miniaturization program that is rolling
through the electronics industry,the
next component that is fast approaching
this horizon is the 0.3mm CSP
• This paper will research the key elements
that influence the 0.3mm CSP deposition
process.
• Process design factors such as solder paste
stencil design and substrate will be fully
investigated.
• The impact of typical fabrication defects
associated to the fabrication of stencils will be
observed to ensure that an authentic picture
is created and not one that belongs in a
laboratory.

With the advent of widespread lead-free soldering,the issue of copper erosion has surfaced as a major quality concern when
soldering RoHS compliant through-hole devices. Many contract electronic manufacturers and original equipment
manufacturers who have implemented lead-free soldering in production volumes have experienced the phenomenon of
copper dissolution. The ability to control this issue is paramount to assuring long-term product quality.
Many circuit board designs are predominately SMT while also containing interconnection hardware,displays and other
through-hole components. This variation in thermal component mass often requires elongated solder dwell times which
exacerbates the effects of copper erosion immediately adjacent to through-hole solder pads and plated thru-hole barrels.
Lead-free wave soldering of through-hole devices often results in a greater occurrence of first-pass solder defects due to the
differences in wetting and flow characteristics of lead-free versus conventional tin-lead solder alloys. This generally results
in a greater propensity of post-wave soldering rework and repair often performed with a static solder pot or fountain-based
soldering system with limited control over critical process parameters other than solder pot temperature,contact time and
solder flow rate.
Mini-wave selective soldering systems employing advanced solder delivery technology,solder nozzles designed for
optimized solder flow,and variable tilt angle extraction,provide an alternative for optimal solder joint formation while
minimizing copper erosion and solder bridging for a range of printed circuit board interconnection applications.
This paper addresses mini-wave application considerations such as component layout and the resulting effects on solder
nozzle design as well as other design for manufacturability considerations. The proper selection of solder nozzles and
process parameters,together with several case studies,will be reviewed to assure optimum solderability critical for lead-free
soldering applications. Proper understanding of system aspects including flux deposition,preheating techniques,solder
application and nozzle design are addressed to insure complete knowledge of the selective soldering process and successful
mini-wave applications.

C4NP (Controlled Collapsed Chip Connection-New Process) is a novel solder bumping technology developed by IBM and
commercialized by Suss MicroTec. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated
and reusable glass templates (molds). Mold and wafer are brought into close proximity and solder bumps are transferred onto
the entire wafer in a single processing step. The technology is capable of fine pitch bumping while offering the same alloy
selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost solution for both,finepitch
FC in package as well as large pitch / large ball WLCSP (wafer level chip scale package) bumping applications.
Solder Transfer is the key process step in C4NP technology. Wafer with capture pad and mold with filled solder is heated and
brought together at a specific temperature. This paper provides a summary of impact evaluation of wafer and mold peak
temperatures during solder transfer process. We discuss intermetallic structure of UBM and solder as well as chip pull
strength and fracture mode. We will also show the reliability results of C4NP Lead Free bumps transferred at several
different transfer temperatures and compare it with the Electroplated High Lead solder bumped high-end logic devices. The
data in this paper is provided by IBM’s packaging operation at the Hudson Valley Research Park in East Fishkill,NY