The motivation for developing higher density IC packaging continues to be the personal entertainment and the portable
handset markets. Consumers? expectations are that each new generation of products be smaller,thinner,lighter in weight and
furnish greater functionality. The challenge electronic manufacturers face when competing in the global marketplace is to
offer a product that will meet all functional and performance expectations without increasing product cost. To address the
need for more functionality without increasing product size,a number of companies have adapted various forms of multiple die
3D packaging. A majority of these early,multiple function devices relied on the sequential stacking of die elements onto a single substrate interposer using a conventional wire-bond process. Because the wire-bonding of multiple tiers of uncased die is rather specialized and the die used may have had relatively poor wafer-level yields,overall manufacturing yield of the stacked-die packaged devices have not always met acceptable levels.
The information presented in this paper focuses on the stringent qualification requirements for a very-thin,vertically configure dµPILR package developed for high-volume memory and mixed function products. A key advantage of this innovative package-on-package (PoP) configuration is that each layer of the package can be pre-tested before joining. This capability greatly improves the overall manufacturing yield and the functionality of the final package assembly is assured. The material developed for this program will outline current environmental expectations for multiple function packaging for hand-held and portable electronic applications and detail the qualification test results for a number of memory variations using this unique,vertically-stacked package technology.

The continued drive for more compact and lightweight handheld mobile devices has forcibly pushed the electronics assembly industry to look for novel packaging and assembly technologies. One of the newest advances in recent years is for semiconductors to be stacked,one on top of the other,in a single package. This die stacking allows system designers to take advantage of the often more readily available “Z” axis of the cubic area while saving on the valuable “X” and “Y” square dimensional space on PCB layouts.
Stacking chips in a package is one method to realize this concept,forming the Stacked Chip Scale Package (SCSP) (Figure 1) and the Integrated Devices Circuit (IDC) manufacturers are responsible for building these units.
Figure 1. Stacked Chip Scale Package
As can be seen from the above diagram,this package is simply another area array package to the PCB assembly house,which requires no changes to existing assembly technology.
This paper focuses on a newer alternative to stacked chip scale packages. This technology involves the novel design of a bottom package containing a high performance logic device to receive a mating top package typically containing high capacity or combination memory devices to form the PoP structure (Figure 2). The key difference here is from the assembly perspective,as the assembler will inherit the assembly process. The driver in adopting this application is cost-effective miniaturization for logic & memory integration.

This paper discusses laser micromachining of thin films. In particular,recent developments on high capacitance,large area,thin,flexible/rollable embedded capacitors are highlighted. A variety of flexible nanocomposite thin films ranging from 2 microns to 25 microns thick were processed on copper or organic substrates by large area (330 mm × 470 mm,or 495 mm X 607 mm) liquid coating processes. SEM micrographs showed uniform particle distribution in the coatings. Nanocomposites resulted in high capacitance density (10-100 nF/inch2) and low loss (0.02-0.04) at 1 MHz. The remarkably increased flexibility of the nanocomposite is due to uniform mixing of nanoparticles in the polymer matrix,resulting in an improved polymer-ceramic interface. BaTiO3-epoxy polymer nanocomposites modified with nanomaterials were also fabricated and were investigated with SEM analysis. Capacitance density of nanomaterial-modified films was increased up to 500 nF/inch2,about 5-10 times higher than BaTiO3-epoxy nanocomposites. A frequency-tripled Nd:YAG laser operating at a wavelength of 355 nm was used for the micromachining study. The micromachining was used to generate arrays of variable-thickness capacitors from the nanocomposites. The resultant thickness of the capacitors depends on the number of laser pulses applied. Laser micromachining was also used to make discrete capacitors from a capacitance layer. In the case of sol-gel thin films,micromachining results in various surface morphologies. It can make a sharp step,cavity-based wavy structure,or can make individual capacitors by complete ablation. Altogether,this is a new direction for development of multifunctional embedded capacitors.

The increase in board routing density,decrease the hole-to-hole spacing and lower to 0.30mm. High aspect ration PTH reliability is not the major issue since the plating copper has at least 20% elongation,but conductive anodic filaments (CAF) and laminate crack are to be concerned since the lead-free assembly and the application of fine pitch components. The lead-free assembly will require higher peak reflow temperature of up to 250degree,and the high temperature will cause thermal damage to PCB,on the other hand,the fine pitch component will require very close hole-to-hole spacing and hole-to-trace spacing,these factors will cause PCB to be easy damaged by the mechanical and thermal stress. The article introduces how to evaluate and avoid these risks.

When planning a trip for the first time there is usually a significant amount of planning and preparation involved. First,the destination is chosen that meets the objective (e.g. Las Vegas for a conference). Next,guidebooks and maps are consulted to chart the route,minimize travel time and cost,and avoid pitfalls along the way such as running out of gas,overheating the engine or not having money for the tolls. The same planning process is generally used in many companies to introduce new technologies. Embedded passives are one of those new technologies in which many companies have an interest in implementing. There is a tremendous amount of hype and excitement in available literature related to the use of embedded passives. Most available information highlights the positive aspects of the technology,with a few negatives sprinkled in occasionally. What is missing happens to be the travel guide that helps a development program avoid the roadblocks,detours,and hazards associated with embedded passives. This paper can be one of those guidebooks. It will highlight the difficulties encountered while implementing embedded passives. It will bring to light some of the design and tool issues,as well as the issues of matching material with board fabricator that appeared along the journey. Those items that were successful will also be shared. So make sure your seat belt is fastened,your tray table is in its upright and locked position,and learn from our journey of implementing embedded passives.

Designers of high performance electronics continue to have system requirements that necessitate the implementation of embedded resistors in microelectronic package and multilayer printed circuit applications. The reasons most commonly given for this shift in technology are performance enabling,reduction in form factor,and relief from routing complexity. The advantages realized with embedded resistors make a strong case for implementation in both new and legacy designs. Until recently,thin film resistors with a maximum sheet resistivity of 250 ohms/square were available. This constrained the practical limit of resistor values to about 10k ohms for small form factor packages and limited resistor footprint. The advent of a robust 1000 ohm/square thin film resistor has allowed designers to expand their range of resistors values that can easily
be captured and still maintain a reasonable resistor form factor. Values to 100k ohms and greater are reachable,and when 1000 ohm/square and lower ohm/square materials are used together in multilayer packages,the resistor capture capability can reach into the 90+ percentage.
In this paper,an actual case,the use of multiple sheet resistivities and their practical use,will be discussed. Low ohm/square material,i.e. 10 or 25 OPS,used in combination with the 1000 OPS will be compared to a Bill of Materials with terminating and pull-up/down and the capture potential. The introduction of a 1000 ohm/square thin film embedded resistor material for this and other applications will also be covered.

To better evaluate CAF (Conductive Anodic Filament) growth we have developed a Test Printed circuit board (PCB) with narrow pitch through holes. (THs) This test PCB can evaluate anti-CAF properties by using very narrow pitch TH (wall to wall 0.05-0.10mm) We tested several laminates using this Test Vehicle and found one of the High Tg Halogen-free FR-4 has excellent anti-CAF restraining properties.

As the electronics industry prepares for the possibility of Pb-free Printed Circuit Board Assembly (PCBA) processing without the EU RoHS server Pb solder exemption,many studies continue to focus on attributes of assembly material chemistries,board finishes and processing techniques. These efforts generally target critical components such as ball grid array packages (BGAs) to ensure reliable solder joints that meet operational requirements at time zero and lifetime reliability targets. For consumer products,this approach may address the known failure mechanisms of the subject card,components,and assembly.
For high reliability products,there could be failure mechanisms in Temperature Sensitive Components that extend beyond critical components in BGA packages. These components include SMT aluminum capacitors,tantalum ceramic capacitors,crystals,oscillators,fuses and other components which have temperature limitations on the package body that restrict the peak reflow temperature and the time duration above 217oC. Exceeding these temperature and time limitations may not induce time zero fails,but may reduce the long term reliability of the component. These components have all been classified and specified for Pb-free processing by their suppliers. Users,including designers and assemblers,may consider these components as non-risk components capable of withstanding the Pb-free evaluation peak temperatures of up to 260 oC as set forth for ICs in J-STD-020. Additionally,as part of temperature profiling efforts,most assemblers do not attach thermocouples to these components resulting in an absence of data collection to ascertain specification compliance. As a result,SMT attach profiling protocol does not generally include the specifications of these temperature sensitive components and subsequently,any induced damage may propagate over time. Depending on the lifetime reliability requirements of the product,product owners risk quality and reliability impacts caused by time dependent failures.
This paper examines the risks that temperature sensitive components pose to high reliability Pb-free server product PCBAs and discusses various issues including smaller process windows,profiling methods and accuracy,time zero quality,and expected reliability performance when using these components. Additionally,the intent of this work is to document the need to identify and monitor temperature sensitive components within industry standards,to extend awareness,and to enable designers / card assemblers to adopt optimum design features and processing techniques. The intended result is to help ensure that products can meet specified lifetime reliability requirements.

In this study,thermal cycling tests for samples of different hole-fill percentages and voiding were conducted,and cross sections of the PTH solder joints were performed to evaluate the solder microstructure,intermetallic formation,via hole-fill,and the condition of the PTH metallization and PCB dielectric prior to thermal cycling and at different times during thermal cycling. Different failure mechanisms were observed for solder joints with and without pin protrusion. PTH components with pin protrusion had better through hole-fill and less voids than PTH components without pin protrusion. The effect of hole-fill percentage and voiding on PTH solder joint reliability are discussed in detail.

As new generations of electronic products emerge they often surpass the capability of existing packaging and interconnection technology and the infrastructure needed to support newer technologies. This movement is occurring at all levels: at the IC,at the IC package,at the module,at the hybrid,the PC board which ties all the systems together. Interconnection density and methodology becomes the measure of successfully managing performance. The gap between printed boards and semiconductor technology (wafer level integration) is greater than one order of magnitude in interconnection density capability,although the development of fine-pitch substrates and assembly technology has narrowed the gap somewhat. All viable efforts are being used in filling this void utilizing uncased integrated circuits (flip-chip) and incorporating more than one die or more than one part in the assembly process.
This paper provides a comparison of different commonly used technologies including flip-chip,chip-size and wafer level package methodologies detailed in a new publication,IPC-7094. The IPC document describes the design and assembly challenges for implementing flip-chip technology in a direct chip attach (DCA) assembly. It considers the effect of bare die or die-size components in an uncased or minimally cased format,the impact on current component characteristics and reviews the appropriate assembly methodology. The focus of the IPC document is to provide useful and practical information to those who are mounting bare die or die size components or those who are considering flip-chip process implementation.