High Frequency and Lead-Free laminate materials are finding increased use in the PWB fabrication industry driven by end
user requirements for high-speed signal transmission and lead-free soldering temperatures. Along with these newer materials
has been the need for improved reliability. End users are continually pushing for thermal performance to exceed five solder
floats and exceed 300 cycles to failure on IST testing. The PWB industry,faced with ever increasing reliability requirements
compounded by the fact that these new resin materials are more difficult to desmear and metalize,have become more
concerned with plating adhesion to the copper interconnect and resin material. Concerns over interconnect defects and resin
adhesion of the copper are causing fabricators to reinvestigate their metallization technologies. The purpose of this paper is
to provide information on how to improve the adhesion of the copper deposit through a closer study of the critical success
factors influencing the metal adhesion to both the interconnect and hole wall. The research showed that the electroless copper
grain structure,plating rates and desmear parameters have a significant influence on PTH reliability. Specially designed high
layer count test vehicles were employed to quantify the adhesion and overall PTH reliability. The results were verified with
micro section evaluation after multiple solder float excursions and Interconnection Stress Testing (IST). This work validates
the necessity of the metallization process to improve the robustness of the PTH under high temperature conditions.

Solder joint void has been considered a typical phenomenon in electronics assembly. Voids are caused by entrapped gases
produced during flux volatilization during SMT,air entrapment in plated through holes and flux reaction with metal
contaminates during the assembly reflow process. The factors affecting void formation are complex and subjective. It has
been observed that BGAs with 2%Ag (62Sn36Pb2Ag) ball tend to create larger voids in reflow solder joints than eutectic
(63Sn37Pb) ball. This study investigates the effect of different process conditions on void formation in the eutectic and
2%Ag solder joints and their effect on long term (2nd level) reliability.
A series of test vehicle PCBs were populated for 2nd level reliability testing using three different BGA packages (165PBGA,
144PBGA,and 1657 FCBGA). A DOE was designed using three factorials; 1) BGAs were acquired with eutectic balls and
2%Ag balls,2) two reflow profiles were established,245C peak volcano-type profile with 3C/sec ramp and long soak profile
with 204C peak,3) two package preconditioning,60C/60%RH 10days and non-aged.
After SMT assembly test vehicles were x-ray inspected for void distribution and void size. X-ray results showed that large
voids,greater than 35% of the solder joint diameter according to IPC-7095A for class 2,were observed in both eutectic and
2%Ag solder joints assembled using large solder paste volume and reflowed using fast ramp rate to 245C peak temperature.
Approximately 60-250% higher distribution of voids was observed in 2%Ag ball packages than eutectic ball packages. It is
believed that the lower melting of 2%Ag (179C) solder ball can reflow slightly before the eutectic (183C) solder paste,thus
the solder ball collapses or encapsulates more solder paste/flux thus entrapping more gases within the bulk solder and
consequently promoting void formation. The effect of voiding on solder joint shock and thermal reliability was investigated
and discussed. It showed voids generated during board level assembly process do not degrade solder joint reliability.

A common source of defects on area array components is the “ball-in-socket” (or “pillowhead”) defect. This defect is
defined as one or more connections that show physical contact but no wetting or intermetallic connection after reflow. The
defect is difficult to detect on x-ray,and can only really be verified on cross section or if the joint in question is in a location
accessible to visual inspection. Worse,the assembly may pass electrical test,since there may physical contact between the
bulk solder and the metallization on the component lead. The lack of an intermetallic bond results in almost immediate
failure in the field,however.
The same sort of defect can also occur on large quad flat pack components,with the component lead resting on top of the
solder deposit without a metallurgical connection. In this case,the defect is referred to as a “foot-in-mud” defect.
The source of these defects is not always obvious,and little has been written about their prevention. This paper presents an
in-depth examination of the physical causes of this defect type,along with specific steps that may be taken to eliminate it.
There are several potential root causes,but the end result of all is vertical movement of one portion of the component
(tilting),resulting in lack of contact with the land during soldering. Formation of an intervening oxide layer prevents
soldering,even when the two metal surfaces are brought together.
Prevention of these defects relies on good design practices that limit thermal gradients,well-designed reflow profiles and
capable reflow equipment. The specific solder paste used can also have an impact on the appearance of this defect,for
several reasons including the alloy melting behavior,flux activity and rheology,and printing characteristics.

A process called computational reliability modeling is described herein as well as how the reliability predictions from this
modeling approach match experimental data (both lead and lead-free solder). It is described that material simulation is rolled
up to the overall board or system level to predict overall electronics reliability.

By now,most people in the industry understand how complex it is to convert a factory from using a Tin-Lead (Eutectic)
Solder process to a Lead Free process. The implementation of this change requires more than just developing a new process
to replace the current one that companies have spent years optimizing. The Lead Free implementation also brings up a new
challenge in calibrating and adjusting the equipment on the production lines to optimize their performance with the Lead Free
process1. For several years now,Flextronics has been using Automated X-ray Inspection (AXI) as effective test equipment
for the inspection of PCBA solder quality,as well as a process improvement tool. By analyzing the variable measurements
provided by AXI,Flextronics has been able to improve the SMT process2-3. Recently,Flextronics wanted to determine if
there was any difference in the AXI measurements of Lead Free and Tin-Lead solder joints. In order to do so,a Flextronics
team used AXI to measure two types of solder or “Test Vehicles:” a Test Vehicle that consisted strictly of Lead Free solder
joints/processes and a Test Vehicle that consisted strictly of Tin/lead solder joints/processes. Testing was conducted under
two different “Test Conditions.” This phrase refers to the manner in which the equipment was calibrated. Under Test
Condition #1,the AXI machine was calibrated with a Lead Free Calibration and Adjustment (C&A) panel. Under Test
Condition #2,the AXI machine was calibrated with a Tin/Lead C&A panel.
The objective of this study was to:
(1) Assess the current AXI Gage Repeatability & Reproducibility for Lead Free Test Vehicle with Lead Free Test
Condition.
(2) Compare and correlate several measurements,including BGA Ball diameter,BGA Ball Thickness,Fine Pitch
Gullwing Heel Thickness,Center Thickness,and Fillet Length,and Resistor 0402 Pad Thickness,for the two types
of Test Vehicles (Lead Free and Tin/Lead) under both the Lead Free and Tin/Lead C&A Calibration Test
Conditions.
The Test Vehicle boards contained 12 BGAs and two FPGullwing devices with a pitch size of 16 mils. More than 240,000
data points were collected for the study. We analyzed the data collected for BGA diameter,BGA Thickness,Fine Pitch
Gullwing Heel thickness,Center thickness,and Fillet Length,and Resistor 0402 pad thickness using the SPC tool MINITAB
and its Mood’s Median Test tool. The results showed a statistical difference for most of the measurements under both test
conditions,Lead Free and Tin/Lead C&A. The majority of the differences for the measurements averaged in the range of 5%
to 10% for the same type of Test Vehicle boards under the different Test Conditions.
The AXI test results not only report attribute data; it also provides variable data (the actual numerical measurements). With
the variable data obtained from this automatic test method,the AXI can be used as a good SMT process improvement tool,as
well as a tool for process defect detection. The variable data has been used to help Flextronics effectively control its SMT
processes. Based on our studies,we found that it is better to test Lead Free or Tin/Lead product boards with corresponding
test condition. For example,the FPGullwing average open signal of a Lead Free board using Test Condition #2 should be
16.5% higher than when using Test Condition #1. The FPGullwing average open signal of the Tin/Lead board using Test
Condition #1 should be 15.5% lower than when using Test Condition #2.

No two printed circuit boards look exactly alike. Even across two adjacent boards on an assembly line,one can find
significant differences arising out of normal process variation – the components and the boards can change color,size and
surface markings. A key challenge for inspection systems is to automatically handle such allowable variation,and distinguish
it from other variations that constitute defects.
Automated optical inspection (AOI) systems have emerged as an important test strategy in printed circuit board
manufacturing to detect defects. Typical AOI systems depend in large measure on heuristics-based (trial and error
experimentation) data as the means to establish typical conditions,the degree of normal variation,the thresholds for nominal
pass/fail conditions,the lighting/camera conditions to best view the object,and the parameters for providing variable
measurement data. The use of empirical processes is a sound basis to make decisions where the sample population being
employed is large enough to mimic the whole. However,user assessments of heuristics require skill and experience of
programmers. As a result,the competency of empirical methods is built up over time and over volume by basing ‘goodness’
criteria on historical values and historical volumes,as seen through the filter of user judgment. Where time and volume are
insufficient to establish stable norms,where user judgment of good and bad are questionable,or where variation of the
elements of the printed circuit board is significant,it becomes difficult to effectively deploy heuristic-based programs.
In this paper,we present a new technology called ‘Configural Recognition’ that provides built-in tolerance to normal process
variation. The technology was initially developed at the MIT Artificial Intelligence Laboratory for applications such as
natural scene classification,face recognition,and trademark logo search. In these applications,normal variation is a
significant and challenging problem for standard computer-vision systems. The technology is grounded in studies of how
humans visually recognize objects.
Over the past six years the technology has been employed for the task of printed circuit board inspection and process control.
The benefits of the technology in the PCB domain are its native ability to recognize PCB artifacts without re-sensitizing the
objects under test,thus eliminating or reducing the necessity of establishing test norms A second benefit is that as variation is
a known entity and accepted as an inevitable but compensated activity,far fewer examples need be used to generate a PCB
test program. Finally,the technology allows for the optical-inspection system to make the leap from finding defects to
providing reliable and repeatable variable measurement data with the same ease of use.

Consistently achieving acceptable wave solder through-hole fill on thick boards is a well-known process challenge,but the
introduction of lead free solders has created additional difficulties. There are many reasons why one might achieve lower fill
with lead free solders and there is much room for improvement in flux materials and process development,but unnecessary
scrap and rework may be avoided by allowing lower barrel fill in some cases.
Most OEMs have a waiver process to allow lower barrel fill than required by IPC-A-610D Acceptability of Electronic
Assemblies for individual holes,but it seemed critical to gather more information for lead free solders in order to support the
possibility of lowering the fill requirements for more boards and components by class. This study updated the previous work
that had been done on through-hole reliability by considering joints made with Sn-3.0Ag-0.5Cu (SAC305) solder and a range
of fill percents,including lower fill percents than are required by IPC-A-610D.
SAC305 through-hole joints (with components loaded) were soldered on 0.062",0.097",and 0.130" thick boards,with fill
percents between 10% and 100%. These boards were subjected to thermal cycling,shock or vibration. After the stress
exposure,the pull strengths of the joints were measured.
The data showed that pin wetted length correlates well with the pull strengths of through-hole joints for different PCB
thicknesses. Shock and vibration were the most detrimental stressors in the range tested. Minimum fill requirements were
determined,based on board thicknesses and load per pin. This work has shown that lower fill levels than are sometimes
required by IPC-A-610D will produce reliable SAC solder joints.

The New England Lead-free Electronics Consortium is a collaborative effort of New England companies spanning the
electronics supply chain,sponsored by the Toxics Use Reduction Institute,the U.S. EPA,and the University of
Massachusetts Lowell. The consortium has completed and published the results of two phases of manufacturing and testing
of lead-free Printed Wiring Boards (PWBs) with the goal of achieving zero-defect lead-free soldering processes with
comparable reliability to that of leaded solder processes. Phase I examined various solder alloy combinations and reflow
profiles,while Phase II focused more broadly on processing parameters,utilizing a mix of component types and finishes in
combination with five different PWB finishes,two reflow atmospheres (air and nitrogen) and three solder paste compositions
based on the same Sn3.8Ag0.7Cu alloy.
Phase III efforts began in August 2004 and will be completed by November 2005. The objective for Phase III testing is to
focus on implementation issues by simulating an actual production board for parameters such as board layers,board size,and
component density. The Phase III PWB is a twenty layer board with components on both sides,and populated with 1,750
components. Thirty-six PWBs were built and inspected to IPC 610 D standards by Benchmark Electronics in April 2005.
The PWBs underwent thermal cycling at Raytheon Reliability Labs test facilities and Highly Accelerated Life Testing
(HALT) at Teradyne test facilities. Pull testing was conducted at the University of Massachusetts Lowell. In this paper,the
authors will present the results of Phase III efforts,including the PWB interconnect stress test,test coupon failure mode
analysis,visual inspection,thermal cycling,HALT,and pull tests.

For this study,researchers from the University of Toronto produced samples of Sn-Pb solder,with additions of bismuth,
solidified at controlled cooling rates. The microstructure of the various Bi content and cooling rate combinations is analyzed.
Limiting conditions for the occurrence of the Sn-Pb-Bi ternary eutectic are discussed. A team from Celestica produced two
sets of test vehicle assemblies using both Pb-free and eutectic SnPb solder. The first set of assemblies includes combinations
of three PWB surface finishes (OSP,Immersion Ag,ENIG) and three component lead finishes (Sn-Pb,Sn-Bi,Ni-Pd-Au).
Microstructures,intermetallic type,composition,and thickness after assembly,aging,and 0°C to 100°C thermal cycling were
studied. Pull testing was performed on QFPs and TQFPs to evaluate the tensile strength of solder joints as assembled and
after thermal aging and vibration conditioning. The second set of assemblies was subjected to 6000 ATC cycles 0C to 100C.
Results are provided for TQFP 0.5 mm and TQFP 0.4 mm devices on ENIG boards. The conclusions on combinations of
solder pastes,surface finishes and component terminations are discussed.

Flexible circuit interconnects for ultrasound transducer applications are among the most difficult to fabricate and make good
representative circuits for medical applications. The polyimide dielectric can be as thin as 12 micron. They often contain
ultra-high density regions that are push the edge of currently available technology. Lines and spaces can be as small as 20 to
30 micron,and via diameters can be as small as 25 micron. The interconnects are typically fabricated starting with
adhesiveless copper on polyimide flexible substrates manufactured using sputtering and electroplating techniques. High
performance polyimides provide mechanical and thermal stability needed to metallize thin dielectric without significant
wrinkling or creasing. The availability of thin copper and smooth interfaces facilitates fine-line etching and high density
features. Good adhesion is critical to ensure fine-line features remain intact throughout the fabrication process. Peel strength
exceeding 6 lb/in is achieved by pretreating the polyimide surface with plasma and applying a suitable tiecoat metal between
copper and polyimide. Laminate dimensional stability after etching and heating exceeds the IPC specification and promotes
good alignment and registration of circuit features. Fine-line features imply strict copper quality requirements. Pinholes
represent an important aspect of copper quality. Systematic analyses have been done to classify pinholes and link different
types to their likely causes. The classification scheme and detailed analyses serve as a basis for pinhole quality control in the
manufacturing environment. The approach has been used to help reduce pinholes and serves to allow rapid containment if
pinholes become an issue.