During the solder reflow processes many reactions occur. There is the reduction of oxides on the metal surfaces,metal dissolution,wetting to different surfaces,and intermetallic compound formation between the bulk solder and the metals being soldering. The intermetallic compound (IMC) is necessary for good solder interconnections. However an excessive IMC may raise solder joint reliability concerns due to its brittle nature. Therefore,a proper IMC thickness is critical for solder joint integrity. The amount of IMC formation is a function of reflow time (Time above Liquidus) and temperature (Peak Temperature). In a Pb-free process,both reflow temperature and time can increase,possibly increasing the thickness of intermetallic formed. During thermal shock,thermal aging or thermal cycling,IMC will grow as well.
The purpose of this study was to investigate the effects of reflow time,reflow peak temperature,and thermal shock on IMC thickness. Four different sizes of chip resistor (1206,0805,0603,and 0402) were attached to OSP surface finish boards with Sn-3.0Ag-0.5Cu (SAC305) solder alloy paste. Traditional Sn-37Pb eutectic solder paste was used as the control in this study. Nine reflow profiles for SAC 305 and nine reflow profiles for SnPb were developed with three levels of peak temperature (12°C,22°C,and 32°C above solder liquidus temperature,or 230°C,240°C,and 250°C for SAC 305; and 195°C,205°C,and 215°C for SnPb) and three levels of time above solder liquidus temperature (30 sec.,60 sec.,and 90 sec.). Half of the test vehicles were then subjected to air-to-air thermal shock conditioning from -40 to 125°C for 500 cycles. IMC thickness was measured using Scanning Electron Microscopy (SEM) with Energy Dispersive Spectroscopy (EDS). The results show that the IMC thickness increases with higher reflow peak temperature and longer time above liquidus together with thermal shock testing.

The pressure on manufacturers of electronic devices to continually reduce the cost of products has continued,despite the challenges of higher cost lead-free production. In many cases assemblers have been forced to attempt to build the new leadfree assemblies using the same equipment,and without increasing the cost of components and laminates. While many manufacturers have considered reliability data from materials suppliers and independent test houses,many have not considered the reliability impact on their own particular assemblies. This paper discusses the potential effect on the reliability of a lead-free assembly in relation to the laminate used and the process parameters.

The pressure on manufacturers of electronic devices to continually reduce the cost of products has continued,despite the challenges of higher cost lead-free production. In many cases assemblers have been forced to attempt to build the new leadfree assemblies using the same equipment,and without increasing the cost of components and laminates. While many manufacturers have considered reliability data from materials suppliers and independent test houses,many have not considered the reliability impact on their own particular assemblies. This paper discusses the potential effect on the reliability of a lead-free assembly in relation to the laminate used and the process parameters.

Work on assisting China's Ministry of Information Industry (MII) to assess the performance of a solder paste using the China alloy Sn3.0Ag0.5Cu0.019Ce (SACCe) was completed. Two Indium fluxes were incorporated as controls. Ce showed no effect on paste printing,slump,or probe testability on flux residue for SAC system. The difference between SACCe and SAC mainly resides in soldering. SACCe exhibits a slightly lower solder beading rate,comparable voiding,a considerably higher tombstoning rate,and is more prone to oxidation hence wets poorer under harsh reflow conditions. No difference in IMC structure or growth rate can be discerned for joints formed on either Cu or NiAu. Overall,China alloy is acceptable in reflow applications. The paste made from the China alloy exhibits a poorer print and a considerably narrower reflow window than
the two paste controls.

There are many issues to be considered in the manufacturing of state-of-the-art electronic products. Today's electronic devices,whether based on flexible (FPC) or rigid (PCB) printed circuit boards,require higher density and tighter tolerances
due to the ever increasing demand of miniaturization and function integration. Depaneling of modern circuits requires that sensitive components are not damaged,close tolerances are maintained and contamination caused by conventional mechanical techniques is avoided. Flex and rigid-flex printed circuit boards are increasingly used offering the ability to resolve three dimensional structural issues and high density electrical interconnection. Mechanical stress placed on flexible or rigid substrate materials by mechanical routing or punching equipment is disadvantageous with regard to accuracy,burr formation and reliability.
We have developed and qualified laser technology based on CO2 laser cutting,meeting today's challenges in the singulation of printed circuit boards. Non-contact processing with a laser means no mechanical stress on the flex or rigid board or its components,no burr or debris and no extra costs for tooling. Smallest tool size of a focussed laser beam is equivalent to highest precision allowing for component placement closer to the edges of a board and increasing the net usable area on a panel. This paper will focus on the results achieved in depaneling of circuits applying a CO2 laser source.

With the introduction of lead free electronics assembly worldwide,greater concerns are raised over factory control of materials and processes. Due to the mix of both leaded and lead free production,greater care must be introduced to ensure proper reflow process control along with data logging for product traceability. Reflow profiles must be more precise in a lead free process since the reflow temperatures of the lead free materials can approach the temperature tolerance of some of the components.
This paper evaluates the introduction of automatic reflow process control in both leaded and lead free environments by the use of bar code readers and redundant process monitoring. The use of the latest automation technology in reflow will
generate the ability to ensure assemblies are reflowed with the proper profile with minimal or no operator intervention along with redundant process monitoring for process control. All data generated can be gathered for individual product traceability and integration of statistical process control. Data will be presented on the implementation,operation,and control of introducing these technologies into a reflow environment.

As technology progresses,electronic components that do bigger and better things are hitting the market. At the same time,the size of the PCB is shrinking. While circuit board designers could resolve the issue by building multiple boards into products to accommodate the additional components,they instead are opting to squeeze them onto a single PCB.
To fit more components in a smaller area,designers decrease the size and spacing of test targets commonly used in bed-of nails fixtures. These test targets allow electrical access to the UUT. The challenge is to hit these smaller targets and still achieve accurate test results. To accomplish this,it is only logical that test probes also need to be smaller. While other types of ATE,including flying probes,X-ray,built-in self-test (BIST),boundary scan software,and optical inspection,combine to enhance the testing of high-density PCBs,the bed-of nails fixture continues to offer the best combination of speed and test coverage in a high-volume manufacturing environment. Since the beginning of automated PCB testing,designers have pushed fixture and probe manufacturing companies to build a better bed-of-nails fixture. However,any new product innovations must be balanced with design for test (DFT) guidelines that have evolved over time to keep pace with the latest advances in PCB and fixture manufacturing. The challenge is getting everyone in the design,manufacturing,and test departments to coordinate their efforts and agree upon the guidelines.
A solution was needed to solve probing issues that were starting to make waves in the in-circuit,bed-of-nails test world. The problem was the reluctance of test managers and technicians to use the “fragile” .050 (1.27) center probes and the insistence of test board designers to put test points on .050 (1.27) and closer centers. The probes designed for .050 (1.27) centers were smaller,harder to work with,had lower spring forces and damaged more easily compared to the widely accepted .100 (2.54) and .075 (1.91) center probes. The new test probe concept was conceived and initially released in February 1998 as a solution.
While the concept of socketless probing isn’t new,the technology wasn’t widely used throughout the industry until the growing demand for smaller test targets started calling for the use of smaller,more delicate test probes. Now,socketless
technology is widely recognized for its capability to use larger,longer lasting probes on high-density PCBs. This is made possible by joining two parts: a probe and a termination pin. In the example shown in Figure 1,the modified interconnect receptacle at the bottom of the probe tube fits securely onto the interconnect pin at the top of the termination. This effectively removes the conventional socket from the system reducing the overall diameter of the probe and thus allowing that same probe to be mounted on closer centers.

A new low cost,simple and repeatable production test method for measuring signal loss of printed wiring board (PWB) interconnects is discussed. The method uses Time Domain Reflectometry (TDR) to measure the transition duration of a step pulse through the PWB interconnect to determine the loss. The loss is presented as an “Equivalent 3dB Bandwidth”. Signal components with frequencies higher than the Equivalent Bandwidth frequency will incur more than 3 dB of loss passing through the interconnect. The method presents the total interconnect loss and does not describe loss components individually (e.g.,dielectric loss and skin effect loss,etc.). This paper describes the specific process of measurement,a metrology capability assessment,and study results demonstrating the method’s ability to use the loss measurements to differentiate among PWB materials and structures.

As the electronic industry is moving to lead-free PWB final finishes and high density circuit boards,the widely used PWB finish,SnPb HASL,has to be replaced with a lead-free and coplanar PWB finish. This transition has already occurred for
many commercial products as of July,2006. Long-term,high reliability products such as in the Telecom industry are still evaluating the reliability of these lead-free finishes. The popular choices for replacing HASL are OSP,ImAg,ENIG,and
ImSn. Among these lead-free finishes,ImAg and OSP are the preferred finishes for many applications,while ImSn and ENIG are used for niche applications. Extensive testing and reliability assessments have been performed on the four lead-free PWB finishes. However,very little attention has been paid to the corrosion resistance of the lead-free PWB finishes once they are field deployed. This is partly due to the fact that the traditional board finish,HASL,has excellent corrosion resistance due to its thick coating and inherent corrosion resistance. In this work,the corrosion resistance of the lead-free PWB finishes has been evaluated using a highly accelerated mixed flowing gas test. We have correlated the extent of corrosion after test to samples kept in field locations around the world for several years,with emphasis on understanding impact of corrosive field conditions on lead-free PWB finishes,especially for telecommunication products with expected service life of 10-20+ years. Not surprisingly,currently used accelerated corrosion test conditions have been shown to be inadequate to challenge products in harsher environments. A comparison will be made between current testing standards and our test conditions. For severe corrosion conditions,several new failure modes associated with the lead-free PWB finishes
will be reported and their relevance to field deployed product will be discussed. The impact of the corrosion on the long-term reliability of the electronic devices will also be discussed.

Planar microvoids have been observed on second level interconnections between solder metallizations and copper lands on PCB boards with immersion silver surface finish. These planar microvoids differ in size and density from the more
common process voids that are found in solder joints. However,unlike the process voids,these planar microvoids reduce the reliability margin by accelerating crack propagation during thermal cycling. Therefore,desired target limits on the density of microvoids of different sizes are established. Monitoring of microvoids observed during PCB assembly production correlates the occurrence of microvoids to “caves” found in the copper land underneath the
immersion silver coating on the bare PCBs of the same production lots. A mechanism is proposed to explain how the caves lead to microvoids during the reflow process. While a thick silver coating and a rough copper substrate were
attributed as probable causes for microvoids in a previous study,a DOE is conducted in this study using a commercial immersion silver process,to evaluate these two factors together with silver bath chemistry and PCB substrate. There
are no caves found in any of the conditions in the DOE,even for an extremely thick silver coating (more than 3 microns). Although the thick silver tends to have a slightly higher microvoid density,it is still well below the desired target limits,
indicating the occurrence of microvoids is also chemistry dependent.