With the introduction of lead free electronics assembly worldwide,greater concerns are raised over factory control of materials and processes. Due to the mix of both leaded and lead free production,greater care must be introduced to ensure proper reflow process control along with data logging for product traceability. Reflow profiles must be more precise in a lead free process since the reflow temperatures of the lead free materials can approach the temperature tolerance of some of the components.
This paper evaluates the introduction of automatic reflow process control in both leaded and lead free environments by the use of bar code readers and redundant process monitoring. The use of the latest automation technology in reflow will
generate the ability to ensure assemblies are reflowed with the proper profile with minimal or no operator intervention along with redundant process monitoring for process control. All data generated can be gathered for individual product traceability and integration of statistical process control. Data will be presented on the implementation,operation,and control of introducing these technologies into a reflow environment.

As technology progresses,electronic components that do bigger and better things are hitting the market. At the same time,the size of the PCB is shrinking. While circuit board designers could resolve the issue by building multiple boards into products to accommodate the additional components,they instead are opting to squeeze them onto a single PCB.
To fit more components in a smaller area,designers decrease the size and spacing of test targets commonly used in bed-of nails fixtures. These test targets allow electrical access to the UUT. The challenge is to hit these smaller targets and still achieve accurate test results. To accomplish this,it is only logical that test probes also need to be smaller. While other types of ATE,including flying probes,X-ray,built-in self-test (BIST),boundary scan software,and optical inspection,combine to enhance the testing of high-density PCBs,the bed-of nails fixture continues to offer the best combination of speed and test coverage in a high-volume manufacturing environment. Since the beginning of automated PCB testing,designers have pushed fixture and probe manufacturing companies to build a better bed-of-nails fixture. However,any new product innovations must be balanced with design for test (DFT) guidelines that have evolved over time to keep pace with the latest advances in PCB and fixture manufacturing. The challenge is getting everyone in the design,manufacturing,and test departments to coordinate their efforts and agree upon the guidelines.
A solution was needed to solve probing issues that were starting to make waves in the in-circuit,bed-of-nails test world. The problem was the reluctance of test managers and technicians to use the “fragile” .050 (1.27) center probes and the insistence of test board designers to put test points on .050 (1.27) and closer centers. The probes designed for .050 (1.27) centers were smaller,harder to work with,had lower spring forces and damaged more easily compared to the widely accepted .100 (2.54) and .075 (1.91) center probes. The new test probe concept was conceived and initially released in February 1998 as a solution.
While the concept of socketless probing isn’t new,the technology wasn’t widely used throughout the industry until the growing demand for smaller test targets started calling for the use of smaller,more delicate test probes. Now,socketless
technology is widely recognized for its capability to use larger,longer lasting probes on high-density PCBs. This is made possible by joining two parts: a probe and a termination pin. In the example shown in Figure 1,the modified interconnect receptacle at the bottom of the probe tube fits securely onto the interconnect pin at the top of the termination. This effectively removes the conventional socket from the system reducing the overall diameter of the probe and thus allowing that same probe to be mounted on closer centers.

A new low cost,simple and repeatable production test method for measuring signal loss of printed wiring board (PWB) interconnects is discussed. The method uses Time Domain Reflectometry (TDR) to measure the transition duration of a step pulse through the PWB interconnect to determine the loss. The loss is presented as an “Equivalent 3dB Bandwidth”. Signal components with frequencies higher than the Equivalent Bandwidth frequency will incur more than 3 dB of loss passing through the interconnect. The method presents the total interconnect loss and does not describe loss components individually (e.g.,dielectric loss and skin effect loss,etc.). This paper describes the specific process of measurement,a metrology capability assessment,and study results demonstrating the method’s ability to use the loss measurements to differentiate among PWB materials and structures.

As the electronic industry is moving to lead-free PWB final finishes and high density circuit boards,the widely used PWB finish,SnPb HASL,has to be replaced with a lead-free and coplanar PWB finish. This transition has already occurred for
many commercial products as of July,2006. Long-term,high reliability products such as in the Telecom industry are still evaluating the reliability of these lead-free finishes. The popular choices for replacing HASL are OSP,ImAg,ENIG,and
ImSn. Among these lead-free finishes,ImAg and OSP are the preferred finishes for many applications,while ImSn and ENIG are used for niche applications. Extensive testing and reliability assessments have been performed on the four lead-free PWB finishes. However,very little attention has been paid to the corrosion resistance of the lead-free PWB finishes once they are field deployed. This is partly due to the fact that the traditional board finish,HASL,has excellent corrosion resistance due to its thick coating and inherent corrosion resistance. In this work,the corrosion resistance of the lead-free PWB finishes has been evaluated using a highly accelerated mixed flowing gas test. We have correlated the extent of corrosion after test to samples kept in field locations around the world for several years,with emphasis on understanding impact of corrosive field conditions on lead-free PWB finishes,especially for telecommunication products with expected service life of 10-20+ years. Not surprisingly,currently used accelerated corrosion test conditions have been shown to be inadequate to challenge products in harsher environments. A comparison will be made between current testing standards and our test conditions. For severe corrosion conditions,several new failure modes associated with the lead-free PWB finishes
will be reported and their relevance to field deployed product will be discussed. The impact of the corrosion on the long-term reliability of the electronic devices will also be discussed.

Planar microvoids have been observed on second level interconnections between solder metallizations and copper lands on PCB boards with immersion silver surface finish. These planar microvoids differ in size and density from the more
common process voids that are found in solder joints. However,unlike the process voids,these planar microvoids reduce the reliability margin by accelerating crack propagation during thermal cycling. Therefore,desired target limits on the density of microvoids of different sizes are established. Monitoring of microvoids observed during PCB assembly production correlates the occurrence of microvoids to “caves” found in the copper land underneath the
immersion silver coating on the bare PCBs of the same production lots. A mechanism is proposed to explain how the caves lead to microvoids during the reflow process. While a thick silver coating and a rough copper substrate were
attributed as probable causes for microvoids in a previous study,a DOE is conducted in this study using a commercial immersion silver process,to evaluate these two factors together with silver bath chemistry and PCB substrate. There
are no caves found in any of the conditions in the DOE,even for an extremely thick silver coating (more than 3 microns). Although the thick silver tends to have a slightly higher microvoid density,it is still well below the desired target limits,
indicating the occurrence of microvoids is also chemistry dependent.

The Pb-free transition in the electronics industry has seen immersion silver emerge as a leading circuit board finish for RoHS compliant processes and products. It is utilized in a wide cross-section of end-use applications,both simple and technically sophisticated. The strengths of immersion silver are numerous; process simplicity at the fabrication level,contact functionality,and durability to multiple reflow cycles are some of the most noteworthy. Recently,the subject of solderjoint microvoiding has been linked to immersion silver processing,and studies of this phenomena have found microvoiding to
present unacceptable risk to the reliability of electronic goods. This work is a continuation of previous publications which explained key root causes of microvoids,along with effective steps at preventing them. The work below presents a review of past findings,additional data confirming the proposed microvoid mechanism,and a substantial volume of production verification data. A direct comparison of this optimized process to alternative immersion silver chemistry is also given.

This paper compares performance of two phosphorus-based flame retardants: poly-(m-phenylene methyl phosphonate) (PPMP) recently introduced to the market and 9,10-dihydro-9-oxa-10-phosphenanthrene-10-oxide (DOPO) the basis of many commercial halogen-free laminates.
Although DOPO is a reactive flame retardant,it is monofunctional and it can be used only with multifunctional epoxy resins. PPMP on the other hand,is a very effective cross-linker and performs as a curing agent. Comparative study with 5 types of epoxy resins and 4 types of co-curing agents showed that both DOPO and PPMP have very high flame retardant efficiency giving V-0 rating at as low as 1 wt. % phosphorus in the formulation. Electrical properties of DOPO and PPMP based laminates are similar. Epoxy resins cured with PPMP show very high Tg which may satisfy FR-5 type laminates. Slightly higher water absorption of PPMP based laminates can be overcome by appropriate curing and better incorporation of phosphorus in the epoxy network.
In the current printed wiring board (PWB) technology where flame retardancy is required tetrabromobisphenol A (TBBA) is the product of choice. Industry has been using TBBA for over thirty years and the product performed well. Currently TBBA is undergoing risk assessment in Europe under new REACH legislation. Human health part of the risk assessment has been completed,but at the time of preparation of this paper environmental part of the risk assessment has not been completed yet because additional studies had been commissioned to address the potential degradation of TBBA and the potential risk to sediment and soil. Not waiting for the outcome of risk assessment,many OEMs announced halogen-free policies if technically feasible alternative to TBBA is identified.

Printed circuit board (PCB) feature sizes are decreasing to support increasing density thrusts for electronic products and packaging. The transition to lead-free products has changed the stress conditions that are generated at the second level
interconnects as a result of “stiffer” lead-free solder joints and greater CTE mismatches between the components and the PCB as a result of the higher assembly temperatures. New laminate materials have been introduced to survive the higher lead-free assembly temperatures. The confluence of all these factors has shifted the primary failure mode in mechanical shock testing for BGA joints from solder fractures in tin lead soldered product to laminate fractures of the metal defined PCB pads (or what Intel calls “Pad Cratering”) for lead-free product.
This paper will review the fundamental drivers that have increased the risk of “Pad Cratering” with the transition to lead-free assembly. In it we will examine and compare the thermal and mechanical material property differences between standard and high Tg FR4 laminate materials after boards are subjected to lead free assembly conditioning. The thermal and mechanical properties will also be compared against the relative “pad crater” response for the test vehicles used in the experiments. This paper will review the metrology methods employed to determine the differences and quantify the results. The paper will also
review the effect of tested design changes on “pad cratering” response. The ultimate goal of the project is to identify key thermal/ mechanical laminate properties and metrologies which can define limits and quantify a product’s susceptibility to “pad cratering”. Additionally,we will examine the sources and extent of variation in the properties for the purposes of providing modeling inputs for the development of predictive mechanical models for “pad cratering”. This paper is a first step in the development process.

The delamination of electrical grade laminates continues to be a vexing problem for the printed circuit board industry. Laminates are commonly tailored to meet specific thickness and dielectric requirements. This will typically involve
modification of the laminate thickness and resin content,leading to the inevitable creation of weak areas within the construction. The current industry standard for delamination testing for electrical laminates requires examination of the
fracture mechanics over a mixture of mode I and mode II type behavior. The mixed mode bending leads to a good deal of ambiguity in the experimental results,complicating investigations to determine the root material properties responsible for delamination failures. To elucidate the true sources of composite delaminations,it is important to begin with an appropriate testing approach. In this paper,we examine several current and experimental delamination test methods. Methods examined include testing in pure mode I,in pure mode II,and in mixed mode I/II. Testing is performed on polymer matrix,e-glass reinforced electrical grade laminates at 23°C. From the analysis,a dedicated testing procedure is presented with the goal of more accurately predicting what values indicate a greater probability of short-term laminate failure. Based on the results,with use of laminated composite fracture mechanics,board constructions and processing conditions can be tailored to limit conditions that place unwarranted stresses on the system,thereby increasing overall laminate performance.

The regulatory measures defined in MIL performance standards that govern production of active and passive electronic components ban the application of pure Sn plated leads for EEE parts. The standards imply that the top coating of the
component leads can contain a maximum of 97% of Tin and a minimum of 3% of Lead as an alloying element. The alloying element reduces the internal stresses present in the pure Tin electroplated coatings and diminishes one of the known causes for whisker growth. However,there are still EEE components on the market that are produced with pure Tin coating on the leads. Some of these components represent an intrinsic part of the successful final product with no viable substitutes.
Experience gained in processing the components,in order to make them flight worthy,highly reliable and whisker free,is used in facilitating a transition from Lead solder to Lead free PCA manufacturing. As a result,a positive trend of removing Lead from the first and second level of electronic interconnects is adopted regardless of the currently applicable exemptions for space industry.
This paper presents experimental data collected on pure Tin plated parts and whiskers grown in the period 1991 –2001 on EEE parts; test results confirming material condition producing whiskers growth trends,dimensional analysis and related processing steps used for annulling generation of whiskers are also performed. The successful processing of the related component,and reported experimental data established grounds for challenging the NASA STD 8739.3 statement on limitations of the minimal spacing from the component body for soldering of leads.
Furthermore,the analysis and qualification test results of the particular non SAC solder considered as a potential replacement of Lead containing solders for space application is elaborated for standard electronic assemblies configurations and thermal regimes. A new prospective,affirmed by qualification test data of using this solder for harness interconnects at cryogenic temperature environment also presented.