Jobs are becoming more difficult to complete to specifications as the complexity of parts increases. With electronic power components getting more advanced everyday reverse pulse technology is offering a great solution in today’s PCB shops. From five years ago or even one year ago there have been many improvements in reverse pulse power supplies. We are seeing very high quality pulses with repeatability. Some manufacturers are integrating intelligent pulse optimization systems into their power supplies. All of these functions increase the reverse pulse process from 30% to 40% better than before.
Prices of these units becoming more affordable and make reverse pulse an even more attractive option to complete those hard to do jobs. With the latest developments in user interface and IPOS in reverse pulse power supplies this integration into your facilities makes an easy transition from your old system to a new system. With today’s reverse pulse power supply technology and our global economy could reverse pulse be one of the solutions for your shop? The constant improvement of electronic components has resulted in many advantages for pulse and pulse reverse power supplies. Some advantages include output currents getting higher to meet the larger scale production facilities needs. The
integration of intelligent pulse optimization systems imbedded into the core software. This enables us to see pulse shape monitoring to achieve repeatability and self optimizing control loops to adapt to bath characteristics. All of these functions give a repeatable waveform and the ability to repeat the process and adjust for changing bath conditions. When working with a delta I 10000A with a slew rate of 100us or less,inductance must be addressed in order to maintain a repeatable pulse form. In order to understand the problem a little better inductance is defined as the following. “The property of a circuit or circuit
element that opposes a change in current flow,thus causing current changes to lag behind voltage changes. It is measured in henrys.” With this in mind there has to be consideration on how to compensate for this in the control of the power supply. IPOS and the latest designed power supplies are using separate voltage and current loops simultaneously this keeping the over and under shoot to a minimum. The next thing to be considered is the connection between the power supply and the plating cell. Depending on the current and the placement of the rectifier either coax cable or twisted pair should be considered. If the distance is not that significant twisted pair would be sufficient. If the distance is significant coax cable should be considered. Coax cable has a lower inductance compared too twisted pair. Most rectifier suppliers should have two types of cooling available when choosing reverse pulse. The first type is air cooled. The size of the rectifier will determine whether the unit will be convection or forced air cooled. The other option will be water cooled. Things to consider when choosing air cooling are the environment it will be placed in,ambient temperature,and cable length. If choosing water cooled,you are able to place the power supply right next to the plating cell to achieve lower inductance. However,water temperature and water quality needs to be considered.

The immersion silver process has become the first choice of final finishing for many original equipment manufacturers (OEM) because of its shortened process flow,good conductivity,even deposition,good solderability and bonding function,and suitability for vertical and horizontal-automated production lines. Some popular immersion silver solutions on the market contain acid that will attack copper to cause circuit break and trace undercutting. The acidity of these processes limit immersion times for silver deposition that can in turn lead to no deposition in the bottoms of blind vias. These processes also frequently use inhibitors or penetrating agents that can contribute to massive voiding and brittle solder deposits. This in turn leads to decreased solder strength.
The shortcomings of these acidic systems are overcome using a mildly alkaline immersion silver. This process has a pH greater than 7 making it possible for longer dwell times that ensures a complete deposition in blind vias. The new process does not contain inhibitors so that the deposited silver possesses higher purity,higher corrosion resistance,lower contact resistance,high soldering strength,and no electromigration. This technology is fully compliant for RoHS and WEEE regulations.

It has been the conventional wisdom of the industry that the predominate board parameter associated with through hole plating is the aspect ratio of the through hole. While this is intuitively understandable,very little has been done to analytically verify the assertion. This paper will explore this hypothesis by developing a first principles flow model using the Navier-Stokes analog for viscous fluids. The first concern is to define the proper flow regime,laminar or turbulent based on the Reynolds Number associated with the process. Once this is established,a proper mathematical model can then be identified. At that point,the governing equations are parameterized and the crucial parameters identified. Faraday’s Law will then be folded into the model to define an algebraic model for electrolytic plating. Finally,an order of magnitude analysis is presented to determine the relative importance of the critical parameters.

Many techniques have been developed to embed capacitors in printed wiring boards (PWBs) these days. The simplest way may be embedding chip capacitors in PWBs. However,since their thickness is over 200 m,the PWBs must be much
thicker. In addition,prepregs or semi-cured insulators for lamination should be prepared with cavities for embedding them.
Polymer composite materials with high-permittivity ceramic filler are a second candidate for embedding capacitors. However this technique needs large area to make decoupling capacitors because of their low capacitance. The best solution
should be embedding thin film capacitors having large capacitance. Now we have developed a novel dielectric insulator and thin film capacitors with the insulator. The capacitor has the structure of metal / insulator / metal (MIM). Both the metal electrodes are copper,and the thin insulator has a high permittivity for large capacitance. The total thickness,including the electrodes and the thin insulator,is less than 50 m; therefore,we need not use prepregs with cavities for capacitor embedding,and the PWB can be kept thin. We also evaluated the electric properties of the thin film capacitor. The capacitance density was 1 nF/mm2 at 1 MHz. The resonant frequency was higher than that of the chip capacitor with the same capacitance. The leakage current was about 1 nA/mm2 at 4 V. We also proposed the process for embedding the thin film capacitors in PWBs.

The global electronics industry is exhibiting a widespread and growing interest in the technology of embedded passives. This interest can be attributed to three primary benefits. First,embedded passives have far less parasitic inductance than discrete components,which enables electrical performance advantages in high speed digital applications. Second,embedding saves surface real estate,which allows for board size reductions. Third,the incremental cost of embedding additional passive components is typically negligible,which suggests the potential for system cost reduction in designs with high passive component counts.
The material we describe here is a high performance embedded passive material intended for embedded capacitor applications. It is a copper-clad laminate which utilizes an ultra-thin,high K-value dielectric material between the copper planes to deliver a capacitance density of over 6 nF/in2.
This presentation will focus on this laminate material and how it can be used to improve electrical performance and reduce board size (by replacing discrete capacitors),and will also address the impact on PCB reliability and system cost.

New interconnect technologies continue to shrink feature size,increase routing complexity and component density in multilayer rigid and rigid-flex printed circuits. Printed circuit fabricators have choices on the technology required to build the multilayer circuits based on the level of the technology required. One innovative technology is sequential lamination where multilayer boards are formed by laminating together plated double-sided or multilayers with blind and buried via interconnections. The sequential lamination manufacturing technique can yield even more significant benefits in performance and circuit processing when combined with embedded resistor features within the printed board. Embedded passive technology allows the resistors to be placed on the same layer as the routed traces reducing the need for microvias. This technology also enables resistors to be placed at an optimum location to reduce the inductance impact of pads,stubs,and coupling. The sequential lamination process in combination with thin film embedded resistors requires a different processing
sequence than conventional multilayer manufacturing with thin film embedded resistors. Materials for embedded resistor can be either stand-alone resistor foil or a resistor laminate. For sequential lamination applications copper foil with a resistive alloy is preferred rather than a resistor laminate material. The copper/resistor foil has very low profile,and small circuit features can be achieved. Consequently,resistors can be fabricated in signal or power ground layers with multiple resistor values and good finished tolerances. The resistor alloys are robust and have low thermal coefficient of resistivity. The resistors maintain their initial values and reliability through the multiple lamination steps and subsequent thermal excursions required by the sequential lamination process.

New interconnect technologies continue to shrink feature size,increase routing complexity and component density in multilayer rigid and rigid-flex printed circuits. Printed circuit fabricators have choices on the technology required to build the multilayer circuits based on the level of the technology required. One innovative technology is sequential lamination where multilayer boards are formed by laminating together plated double-sided or multilayers with blind and buried via interconnections. The sequential lamination manufacturing technique can yield even more significant benefits in performance and circuit processing when combined with embedded resistor features within the printed board. Embedded passive technology allows the resistors to be placed on the same layer as the routed traces reducing the need for microvias. This technology also enables resistors to be placed at an optimum location to reduce the inductance impact of pads,stubs,and coupling. The sequential lamination process in combination with thin film embedded resistors requires a different processing
sequence than conventional multilayer manufacturing with thin film embedded resistors. Materials for embedded resistor can be either stand-alone resistor foil or a resistor laminate. For sequential lamination applications copper foil with a resistive alloy is preferred rather than a resistor laminate material. The copper/resistor foil has very low profile,and small circuit features can be achieved. Consequently,resistors can be fabricated in signal or power ground layers with multiple resistor values and good finished tolerances. The resistor alloys are robust and have low thermal coefficient of resistivity. The resistors maintain their initial values and reliability through the multiple lamination steps and subsequent thermal excursions required by the sequential lamination process.

The reliability of aged and repaired lead-free and mixed lead-free/lead-based solder interconnects is an important issue for electronic equipment manufacturers. As a result of the global transition away from lead driven by government legislation and market pressure,maintained lead-based electronic equipment may need to be repaired with lead-free parts and materials
due to improper labeling or inability to obtain proper replacement materials. An experimental study to examine the reliability of aged and repaired solder interconnects was conducted. Test specimens included thermally aged and non-aged lead-free and lead-based printed wiring assemblies with surface- mount components,including ball grid arrays (BGAs),leadless resistors,and quad flat packages (QFPs). Test specimens were subjected to aging and repair where lead-free and lead-based components and materials were intentionally mixed. Temperature cycle loading was used to examine the reliability of the solder interconnects. Test results show that thermal aging is more detrimental to lead-free solder interconnects than to leadbased interconnects for PBGAs. Further,the failure distribution of the lead-free assembled PBGAs was found to be wider
than the distribution of the lead-based failures.

The reliability of aged and repaired lead-free and mixed lead-free/lead-based solder interconnects is an important issue for electronic equipment manufacturers. As a result of the global transition away from lead driven by government legislation and market pressure,maintained lead-based electronic equipment may need to be repaired with lead-free parts and materials
due to improper labeling or inability to obtain proper replacement materials. An experimental study to examine the reliability of aged and repaired solder interconnects was conducted. Test specimens included thermally aged and non-aged lead-free and lead-based printed wiring assemblies with surface- mount components,including ball grid arrays (BGAs),leadless resistors,and quad flat packages (QFPs). Test specimens were subjected to aging and repair where lead-free and lead-based components and materials were intentionally mixed. Temperature cycle loading was used to examine the reliability of the solder interconnects. Test results show that thermal aging is more detrimental to lead-free solder interconnects than to leadbased interconnects for PBGAs. Further,the failure distribution of the lead-free assembled PBGAs was found to be wider
than the distribution of the lead-based failures.

The purpose of this program was to evaluate the solder joint reliability,using the IPC-9701 standard as a guideline,of PCBAs that were assembled with conventional leaded and ROHS compliant lead free processes and to evaluate the
capabilities of multiple PCBA assembly houses. 6 sample groups of 26 samples each from 3 different suppliers were subjected to a full qualification plan,SEM,cross-sectional imaging and EDX analysis. The groups consisted of lead free
(SAC) test coupons and standard leaded (SnPb) test coupons. The test coupons were populated with surface mount daisy chained dummy components. The component finishes were SnCu and the board finishes were immersion Ag. The coupons were subjected to mechanical strength (lead pull testing,vibration and impact tests),long term reliability (damp heat,temperature cycling and whisker growth tests) and solder joint quality (cross-sectioning,SEM imaging and EDX of
components). The test results were analyzed to compare the capabilities of the 3 PCBA assembly houses and to evaluate the relative differences between the conventional leaded and ROHS compliant lead free processes.