Rarely does a day pass by without a discussion centered on lead free manufacturing and it’s future impact on global
electronics assembly. The WEEE and RoHS directives drafted in January 2003 with a focus on electronic product recycling
and a ban of six hazardous substances in electronics products has created quite an industry buzz. European member states are
responsible for passing their own legislation making the directives law and binding in their respective countries. The WEEE
directive has slipped implementation in many countries as establishing recycling logistics appears to be more difficult than
first thought. On the other hand,RoHS compliance is moving along at a fast pace with many companies finding suitable
solutions and replacements for Sn/Pb solders. Engineers are now faced with optimizing the process variables around these
new material properties. Many recent studies have analyzed the effect / impact of Lead Free solder paste implementation on a
multitude of SMT processes including solder joint strength,wetability of SMD leads as well as pads on the PCB with a
variety of board finishes and solder paste compositions. Hardly a day goes by where you don’t see an announcement about a
new Lead Free implementation Workshop.
This study will focus on the stencil and squeegee blade and their impact on the Lead Free solder paste-printing process. Three
different stencils,three different Lead Free solder pastes,and five different squeegee blades are included in the study. The
Benchmarker II stencil test pattern was used as a tool in the evaluation. Of particular interest is the surface roughness /
smoothness of the stencil squeegee side surface. It is demonstrated that this surface has a dramatic influence on the minimum
squeegee pressure for metal squeegee blades to achieve clean wiping of the Lead Free solder paste from the stencil surface. In
addition to the surface finish of the stencil it was found that the type of Lead Free solder paste and the type of metal squeegee
blade used also played a roll in determining the minimum squeegee pressure to achieve clean wiping of the solder paste.

The trend towards miniaturization has been with us for quite a while,with marketing departments pressuring for ever-smaller
dimensions for everything. A question that arises frequently in this context is as follows: Can we accommodate these
requirements by offering miniaturization in three dimensions rather than the conventional two in PCB design? A positive
answer to this question is now provided through the utilization of embedded passive technology.
In this paper,we present a full flow in comparison between a conventional and 3-D board having the same functionality. The
first board is a conventional two dimensional board 780mm x 290mm large,using 1.6mm FR4 in four layers while the
second board is three dimensional,330mm x 366mm large also using 1.6mm FR4 in four layers. The paper includes the
details of the decisions taken,the design,layout,simulation,and MRP,as well as considerations of purchasing,materials,
assembly,yields,rework,reliability,all summarized in terms of a cost benefit analysis. Additional benefits of this technology
are shown to be the possible reduction in size of some of the testing fixtures such as cycling ovens and testbenches.

Buried sheet capacitance has been used for sometime in sophisticated PCB designs. The ZBC 2000TM patented by the
Sanmina Corporation is a familiar example. Conceptually,this product consists of one or more innerlayers with a two-mil
FR4 core. Each such innerlayer forms a sheet capacitor of approximately 500 pico-Farads per square inch. The original
purpose of the technology was to replace the surface by-pass capacities with an internal alternative and thereby provide
additional outerlayer real estate for routing and active components. Later it was also found that a properly designed buried
sheet capacitor is an effective method for containing EMI radiation.
The purpose of this paper is to analytically investigate the dynamic properties of buried capacitors when incorporated into a
PCB board. Techniques for improving the performance are also examined.

Many articles have been published on the benefit of thin substrates for use as embedded capacitor layers as well as thin film
resistive material for embedded resistors. Until now the utilization of both technologies within a printed circuit design
required the use of separate cores within the PCB. This adds additional thickness to the PCB as well as cost. A new
substrate has been developed to address these issues.
Embedded technologies improve the electrical performance of high speed digital circuits as well as enabling the removal of
SMT discrete components (the ratio of passives to active components is increasing while the available board surface area is
decreasing). By combining capacitance and resistance on the same core,with the resistor foil being supplied on one or both
sides of the capacitor dielectric,these benefits can be realized without increasing the overall number of layers or the substrate
thickness. Also,some unique R-C circuit designs can be formed by utilizing this substrate.
We will discuss the process and design guidelines for using this substrate as well as some possible applications. Also,results
from high frequency testing of PCB test vehicles will be discussed. Future product developments will also be shared.
It will be demonstrated that this new substrate has excellent electrical properties while being able to be readily manufactured
using typical inner-layer processing.

Since early last decade,scientists had succeeded in applying printing-related technologies to create organic field
effect transistors (OFETs) with micron-sized features. This has led to a wide- spread vision of developing printed
electronic products,especially sensors,displays,and low cost wireless products such as radio frequency
identification tags (RFIDs). The market opportunities for many of these applications depend strongly on
materials and manufacturing cost. Towards this end,we have developed a ferroelectric/epoxy nanocomposite
dielectric,whose advantages in terms of processability,low processing temperature,low cost,and versatility
make it quite promising for printed electronic applications. In this paper we present our work to develop low cost
printed capacitors with five micron thick nanocomposite dielectric with a high capacitance density of about 62
pF/sq. mm. with low dielectric loss (approximately 3%) and quite low current leakage.
Solution processed,high capacitance nanocomposite dielectric material was demonstrated as a low cost
insulating material for printed electronics applications. A nanocomposite dielectric consisting of cross-linked
propylene glycol methyl ether acetate and barium titanate (BTO) nanoparticles was developed and utilized as a
printed dielectric. The high relative permittivity (K=35),bimodal nanocomposite system utilized has two
different filler particle sizes 200 nm. and 1000 nm. diameter particles. Due to the nanosize of the BTO particles,
they disperse well in the organic matrix,which makes it possible to use solution-processable methods,such as
pad printing.

Today’s advanced packages for electronics are required to meet a wide range of requirements for reliability,size and cost.
Surface mount technology still prevails in low cost electronics (televisions,VCR’s,washing machines,etc). Most surface
mount IC’s are wire-bonded,molded devices,and not considered “advanced packaging”. The challenges in packaging
increase as the need for portability,performance,or reliability increases. The size and performance constraints of notebook
computers,mobile phones,gaming devices and other handheld portable electronics are drivers,as is automotive electronics.
The mantra “smaller,faster,cheaper” has turned into a fevered battle cry in electronics manufacturing today.
Automated Fluid dispensing is a process found throughout electronics manufacturing. Notable among the applications are die
attach adhesives,wire bond encapsulants,and flip-chip underfills. Materials manufacturers continue to innovate,enabling
new processes to develop,as well as bringing the cost to manufacture down. Traditional needle dispensing is a mature
solution to many of the manufacturing challenges that exist. But a new application method,known as jetting,is breaking
formerly established barriers and enabling new applications that simply were not possible with traditional techniques.
This presentation discusses the physical action of jetting and highlights the fluid parameters that relate to jetting. The main
advantage to jetting arises from the fact that the fluid is imparted with momentum and is actually shot from the nozzle. This
property not only affects the flow rate through the nozzle,but also considerably affects the overall rate of the entire process.
The jetting process is independent of the dispense gap,a highly important parameter in needle dispensing. (The surface of the
substrate is used to pull the fluid deposit from the needle.)
Because proximity to the dispensing surface is a critical parameter of needle dispensing,it is usual for the robot controller to
use precious time moving the needle to the correct Z-location for each deposit. With jetting the robot can literally fly above
the surface and shoot from a distance,eliminating Z-axis motion time as well as many of the dwells and delays used to
account for the flow of the material from the needle.
Additionally,the dimensions of the fluid stream from a jet permit control of the fluid to never-before-possible restricted areas.
Stacked Die,RF shields,and sub-250 micron fillets for underfill are now not only possible but a production reality.
The bulk of underfill processing throughout the semiconductor industry has turned to jetting as a new and improved method
because of its inherent speed and precision. A brief review of the many dispensing applications in electronics will establish
the landscape into which jetting fits. Specific dispensing applications are detailed; with traditional fluid application methods
shown. The impact that the new jetting technology has on cost and productivity is then discussed.

Solder paste dispensing is not a new process. However,today’s microelectronics present a daunting array of technical
challenges to meet deposit size requirements. The need for better paste formulations,more precise equipment,and more
tightly controlled processes is driving paste suppliers and equipment suppliers to develop new methods and materials.
The most challenging solder paste deposits are those smaller than 0.25mm in diameter and today’s electronics demand
such deposits. This paper addresses the process requirements for solder paste micro-deposits in terms of material,
equipment and process variable control required for success in producing 0.25mm and smaller deposits.

Technology requirements within the electronics industry are rapidly driving the miniaturization of and increasing component
densities on the printed circuit board. As a result,assembly equipment must offer increased accuracy capabilities while
delivering both the required high yield and high throughput capabilities.
Typically,dispensing platforms only specify XY repeatability and/or dot placement accuracy,expressed as a sigma value.
These specifications do not include the error associated with positional mechanisms,which greatly contribute to final
accuracy and repeatability. Many factors influence positional accuracy,including the XY gantry,camera calibration,
fiducial teaching errors and camera-to-needle offset calculations.
To determine the true machine capability,including positional accuracy and express it as a Cpk value,a new test method
must be developed to take into consideration all influencing factors. Call it “Total System Accuracy™.” By calculating the
“Total System Accuracy” of a dispensing platform,including material placement accuracy on a substrate relative to a defined
target,it is possible to determine the true platform capability and provide a better understanding of how the product will work
for various applications.

A combined environment testing was conducted for the Joint Council on Aging Aircraft/Joint Group on Pollution Prevention
Lead free Solder project. The purpose of the project was to validate and demonstrate lead free solders as potential
replacements for conventional tin-lead solders used on circuit card assemblies against the requirements of the aerospace and
military electronics community.
The solder alloys tested include: Sn3.9Ag0.6Cu,Sn3.4Ag1.0Cu3.3Bi,Sn0.7Cu0.05Ni and Sn37Pb. These solder alloys
were used to assemble various components on three different printed wiring board test vehicles: manufactured,rework and
hybrid. The test vehicles were subjected to a combined environments test consisting of thermal cycling from –55 to 125
degrees Celsius at a ramp rate of 20 degrees Celsius per minute,dwell at the temperature extremes for 15 minutes and
pseudorandom vibration of 10 grms for the last 10 minutes of the dwell periods. After every 50 cycles,the vibration level was
increased by 5 grms until a maximum of 55 grms was reached. The test vehicles were electrically monitored using event
detectors.
The solder joint failure data of a given component type,component finish and solder alloy were evaluated using Weibull
analysis. The reliability of the lead free solder alloys was compared to the baseline tin-lead (Sn37Pb) solder alloy.

The use of conventional tin-lead (Sn/Pb) solder in circuit board manufacturing is under ever-increasing political scrutiny due
to environmental issues and new regulations concerning lead,such as the Waste Electrical and Electronic Equipment
(WEEE) and the Restriction on Hazardous Substances (RoHS) Directives in Europe. In response to this,global commercial
electronic manufacturers are initiating efforts to transition to lead-free assembly. Lead-free (Pbfree) materials will be finding
their way into the inventory of aerospace and military assembly processes under government acquisition reform initiatives.
Any potential banning of lead compounds could reduce the supplier base and adversely affect the readiness of missions led
by NASA and the DoD. The Joint Council on Aging Aircraft (JCAA)/ Joint Group on Pollution Prevention (JGPP) Lead-
Free Solder Project,a partnership between DoD,NASA and OEMs,was initiated to examine the reliability of Pbfree solders
exposed to harsh environmental conditions representative of NASA and DoD operational conditions. This paper reports
results to date on the JCAA/JGPP consortia -55ºC to +125ºC thermal cycle testing. The main goal of the thermal cycle testing
effort is to generate data from test boards that are representative of IPC Class III High Performance Electronic Products.