We report test results of bending characteristics of flexible printed circuit board,which contributes to the development of
higher density and more sophisticated function of mobile devices and electronic equipment. Our report shows that there is a
correlation between mechanical structure and the bending characteristics of flexible printed circuit boards,and that ultra thin
structure shows excellent performance in bending applications. We also find that elasticity modulus of adhesive plays a key
role in the bending characteristic of flexible printed circuit board. We have utilized the finite element method to evaluate the
strain for investigation of the bending fatigue mechanism. We will report on the study of a formula with which we can
estimate the flexural fatigue life. We also show the analysis result of generated stress when various constructions of flexible
printed circuit boards are bent.

It has been reported by several laboratories that the time to delamination or decomposition of a printed circuit board specimen
at 260°C decreases with the specimen thickness. A temperature gradient across the thickness of the sample within the furnace
of the Thermomechanical Analyzer (TMA) was the suspected cause. Testing laminate specimens with embedded
thermocouples,the temperature gradients within two major brands of TMAs and at several laboratories was determined to be
approximately 2.5 to 3°C per millimeter. This temperature gradient results in a 20°C difference between the top and bottom
of a 7 mm thick specimen. Modifications of the T260 test parameters,such as thermocouple location during the test and
thermocouple calibration procedure are recommended.

A series of electrical plating processes to build various kinds of micro bump arrays on the organic substrates has been developed for non-permanent connections. Copper bump arrays with nickel/hard gold plating on the organic substrate with small pitches have been required for the non-
permanent terminations. Electrical test probes of the semiconductors and micro size components have been demanding reliable micro bumps on the organic substrates for the repeated contacts of more than one million times. Several combinations of the micro hole generation processes and the electrical plating processes have been developed to
satisfy the requirements. The new electrical plating processes are capable of building the micro bump arrays with copper,
nickel and hard gold for pitches smaller than 50 microns on the substrates of FR-4 boards and polyimide films with epoxy or polyimide insulation layers. The plating processes provide broad choices for the shapes and heights of the micro bumps with copper,nickel and gold. Several drilling processes have been introduced to generate small holes with high dimensional accuracy for the exact alignment of the micro bumps on the narrow traces. A series of studies were conducted to review the capability of the drilling process. The whole process has a broad capability for the all kind of organic substrates. A set of design guidelines has been introduced to optimize the productivity.

With the progress of miniaturizing electronic equipment with higher performance,packaging substrates for semiconductor
devices are required to cope with finer patterning and higher wiring density. The semi-additive wiring process has been
needed in place of the conventional subtractive wiring process because the former can achieve higher wiring density than the
latter. To realize high-density wiring,the surface profile is very important. Besides wiring process ability,improvement in
several properties has been required because high-performance and complicated packaging substrates need higher reliability
and lower transmission loss.
A new insulation material for the semi-additive process has been developed in these situations. This new material is
applicable to the semi-additive process and features higher elongation,better dielectric properties,satisfactory plating peel
strength with smoother surface profile,as well as being environmentally friendly.
In generally,most of the thermosetting resins,including epoxy resin,have a fragile nature compare to the thermoplastic resins.
However,this new materials has relatively low modulus and high elongation in spite of using epoxy resin-based material; it
also has a low coefficient of thermal expansion (CTE). The material proved to have enough insulation resistance and
electrical reliability. The transmission loss for the material was smaller because of its lower surface profile. This new material
is expected to find applications as an insulation material for next generation packaging substrates.

We have developed the copper high density wiring formation technology with Cu/photosensitive Benzocyclobutene (BCB) as
a dielectric material,and interconnect technology with Silicon through-hole. The basis is four-layer structures with copper
conductors and BCB dielectric formed on the core substrate. We have adopted stacked via structure as multi-layer and the Si
wafer for core substrate. We selected the metal titanium as an adhesion layer between the conductors and the dielectrics
before copper conductor layer formation. We measured the adhesion strength between conductor metal and BCB using the
90-degree peeling test. The peeling strength becomes stronger than 0.50 kN/m by performing the suitable pretreatment on the
BCB. The core substrate is composed of copper plugs,which connect the front and backside of the wafer electrically. The
copper plugs are 30 µm in diameter and 250 µm depth. We have succeeded in production of plugs without voids and have
confirmed good reliability by THB test and the heat cycle test.
We have also measured and simulated the fundamental transmission properties of micro strip line of Cu/BCB multi-layer
wiring structure and compared with the another dielectric material such as PI and Fluorene. The frequency was swept from
100 MHz to 40 GHz,and two-port parameters such as S11 (reflection) and S21 (transmission) were extracted. The result is that
transmission loss of BCB is maintained about 1.5 dB at 30 GHz,when the line length is 5 mm and the line width and space
are 10 µm /10 µm. It was most excellent in especially high frequency range as compared with other dielectric materials. We
obtained approximately same result also in the simulation. We have confirmed good agreement of transmission properties of
micro strip line structure between simulation and measurement data.

A previously developed ball grid array (BGA) solder joint vibration fatigue life prediction model,which was experimentally
validated by Test Vehicle One (TV1) test data for the BGAs with and without under-filled materials,has been used to
determine the solder joint integrity of BGAs. However,the newly obtained TV2 test results show that this previously
developed life prediction model has a tendency to under estimate the fatigue life of BGA solder joints. Therefore,there is a
need to re-validate the previously developed life prediction model and it then becomes the objective of the present study.
A TV2,on which various sizes of BGA daisy-chained packages with/without under-filled materials (including nonreworkable
and reworkable) are soldered,is designed,fabricated and subjected to random vibration tests with continuously
monitoring the solder joint integrity. Based on the measurement results,a destructive physical analysis is conducted to further
verify the failure locations and crack paths of the solder joints. The previous developed life prediction model combined with
a finite element analysis is re-calibrated by the TV2 test results. This updated model is then recommended to serve as an
effective tool to determine the solder joint integrity of the BGAs (with/without under-filled materials) during vibration. The
determination of the relationship between the BGA solder joint fatigue life and the elastic modulus of under-filled material is
illustrated. The analysis results show that BGA fatigue life exponentially increases as the elastic modulus of under-filled
material increases to a certain threshold value and this relationship can be used to select the under-filled material for
improving BGA solder joint vibration fatigue life.

In this report,the group activity of developing and proposing standard EMC models for numerical EMC simulation is presented. Our group has developed some basic and standard EMC models which contain the essential characteristics of EMC and has discussed about the calculated behaviors. These models can be used for studying EMC and EMC simulation
and for comparing different simulators. The developed models are briefly presented. A model of differential transmission lines,for example recently took up,is explained as an example. The differential transmission line which has a difference in height on the middle of the line was developed to investigate the emission depending on the parameters of line height,line separation,phase of the driver and so on. For example,the contribution of the common and differential mode radiation was
studied by changing phases of the differential drivers. From the calculated results,it is suggested that the emission from the
line was dominated common mode radiation because the emission was almost proportional to common mode voltage of the differential drivers.

The paper will address issues that will impact defect levels and defect spectrum during the transition to lead-free
manufacturing. Since there are exemptions of which product types are mandated to go lead-free,and not all components will
be available in lead-free versions,there is not a clean path to lead-free manufacturing. Both manufacturers that are forced to
go lead-free as well as companies that are exempted will be impacted. This and other issues will have a big impact on the
optimal test strategy. Data of defect levels and defect spectrum from lead-free production will be presented below. The paper
will also address different test and inspection systems’ readiness to test lead-free printed circuit board assemblies (PCBA).

Metal-base printed circuit boards (PCBs),multilayer PCBs and embedded PCBs are constructed with a thin insulation layer.
In these PCBs,particularly those used for Power Electronics,the insulation layer is stressed under a high-strength electric
field. Metal-base PCBs are applied to 100-400 V power circuits for power transistor modules,general purpose inverters and
so on. Since the insulation layer is stressed under a high-strength electric field of approximately 1-3 kV/mm,the reliability of
the insulation layer is important. In order to investigate the migration process,we have studied the behaviour of ionic
impurities in the insulation layer of various PCBs by measuring space charge profiles using the pulsed electroacoustic (PEA)
method. Since space charge behaviour affects the internal field profile,the experimental results should contribute to the
insulation design of PCBs. Consequently,hetero charge accumulated in the vicinity of the electrode in the insulation layer of
two types of metal-base PCBs and two types of Aramid/Epoxy PCBs,and the electric field strength near each electrode are
enhanced two-three times more than the average field strength of 5 kV/mm and 10kV/mm. Two types of PCBs (Glass/Epoxy,
PTFE/Epoxy) do not exhibit significant electric field distortion under 5 kV/mm and 10 kV/mm. After thermal humidity bias
(THB) testing for 20 and 59 hours (DC 1250 V at 85°C and 70% RH),the space charge measurement detected a conductive
region that was formed in the insulation layer near the anode of the metal-base PCB A. Element distribution analysis verifies
that the conductive region is formed due to copper ionic migration. These results reveal that space charge measurement can
carry out a non-destructive observation of the growth of copper migration.

The 2002 International Electronics Manufacturing Initiative (iNEMI) Optoelectronics roadmap anticipated a cross-over in
cost-performance whereby a system using optical transmission of high speed signals would have lower overall “cost” than a
pure electrical system of equivalent function. In 2003,iNEMI formed a task group to investigate this cross-over point via cost
modeling analysis. The activities to date have been to adapt and verify an existing cost model for copper-based PCBs and
develop an electrical backplane technology roadmap to 40 GHz,with logical combinations of bus type,connectors and signal
conditioning chip sets. We are currently reviewing the relevant optical technologies,including optical fiber,fiber flex or
embedded polymer waveguide,optical connectors and transceivers to develop the equivalent optical roadmap. This
presentation will be a work-in-progress report on the iNEMI project activities with the goal of developing cost and
performance models to compare different designs of electrical and optical backplanes.