Many professionals in the electronics manufacturing industry have,or eventually will,face the issue of determining
whether the materials of construction for printed wiring assemblies (PWAs) are compatible with each other for the
products produced,and producing objective evidence of this compatibility. Such a determination may be a
monitoring or changing of an existing in-house manufacturing process,the development of a new manufacturing
process,or determining if assemblies produced by a subcontractor are acceptable. The concept of materials
compatibility can be very broad,depending on what factors are chosen for examination,but is critical to
understanding the reliability of manufactured hardware.
This paper focuses on the use of the IPC-B-52 standard printed wiring assembly as a test vehicle to meet these
needs,with illustrative data from a high reliability avionics manufacturing process,including lead-free evaluations.

The in-circuit test (ICT) of printed circuit boards (PCBs) assembled with Lead Free solder was anticipated to be problematic
by industry test engineers,due to contact failures associated with the perceived lack of pin probeability of Lead Free solder
pastes and fluxes. The introduction of Lead Free processing could potentially present new challenges to the established ICT
process.
A good electrical contact between test probes and test targets on the unit under test (UUT) is fundamental to the success of
ICT. The testing of tin-lead soldered PCBs is a mature process,supported by years of effort,many studies and numerous
improvement projects,carried out on pin probable solder paste,flux development,design for test (DFT),test probe and
fixture design.
A study of Lead Free processing and the impacts to test and inspection equipment was undertaken. All available information
from customer product introductions,test equipment vendors and industry resources was collated and the risks involved in
moving from tin-lead solder to Lead Free solder were identified.
This paper describes the method and experimentation used to investigate ICT probe contact on Lead Free boards. A test
vehicle was designed with different sized test pads and vias and an ICT fixture was manufactured. Process and test
influencing factors were identified,including various Lead Free solder pastes and board finishes. Using Six-Sigma
methodology,a number of experiments were designed,results analyzed and the significance of the experiment parameters
(factors) investigated. Recipes were developed for achieving good ICT probe contact on Lead Free boards.

Reflow profile has significant impact on solder joint performance because it influences wetting and microstructure of the
solder joint. The degree of wetting,the microstructure (in particular the intermetallic layer),and the inherent strength of the
solder all factor into the reliability of the solder joint. This paper presents experimental results on the effect of reflow profile
on both 63%Sn 37%Pb (SnPb) and 96.5%Sn 3.0%Ag 0.5%Cu (SAC 305) solder joint shear force. Specifically,the effect of
the reflow peak temperature and time above solder liquidus temperature are studied. Nine reflow profiles for SAC 305 and
nine reflow profiles for SnPb have been developed with three levels of peak temperature (230oC,240oC,and 250oC for SAC
305; and 195oC,205oC,and 215oC for SnPb) and three levels of time above solder liquidus temperature (30 sec.,60 sec.,and
90 sec.). The shear force data of four different sizes of chip resistors (1206,0805,0603,and 0402) are compared across the
different profiles. The shear force of the resistors is measured at time 0 (right after assembly). The fracture surfaces have
been studied using a scanning electron microscopy (SEM) with energy dispersive spectroscopy (EDS).

Lift-off (fillet-lifting) and land-lifting phenomena,which occur in wave soldering with Sn-Ag-Cu (SAC) solders,depend
on the physical properties of the solder and the laminate material used. A new Sn-Ag-Cu-Ni-Ge (SACNG) solder and
two types of printed wiring board (PWB) laminate materials with higher glass transition temperatures (Tg),lower
coefficients of thermal expansion (CTE) and higher peel strengths at high temperatures have been developed to suppress
fillet- and land-lifting. The SACNG solder and laminate materials have shown excellent reliability in the wave
soldering process and thermal cycling evaluation. Moreover,the valid physical properties of laminate materials for
suppressing fillet- and land-lifting have been investigated by FEM analysis.

Meeting the RoHS directive will require the transition from the historical tin-lead based system of materials to one that
does not contain lead. This is of course is not straight forward as it is impossible to control 100% component material
compositions. It is therefore entirely possible that components with lead finishes will find their way into Lead Free
processes. The concern is that lead contamination occurring in this way results in 1 to 10% level of lead,and that this
lead is not uniformly distributed,but segregates to the grain boundaries and joint interfaces [1]. But what is the effect of
this on thermal fatigue. The work reported here will describe experiments where the lead level in solder joints was
controlled by altering the plating on component terminations and using controlled solder compositions. Microstructural
examination verifies the segregation of lead. The built assemblies were then thermally cycled between –55 and 125ºC for
2000 cycles to assess this effect on reliability. Hot peel tests were also run to simulate problems that may occur is
secondary wave operations where the fillet strength collapses and components can detach with little force at temperatures
above 180ºC. The use of indicator test kits to detect lead were also evaluated on this set of reference samples. This paper
will discuss these results and the likely impact on the industry and the necessary precautions.

The constant drive by designers to create more functionally unique products has challenged the assembly community for
some time. As a result,many processes have been developed under the “Necessity is the Mother of Invention” rule. For EMS
providers to develop unique adaptations to their processes,they must work closely with their suppliers of equipment and
materials. Some requirements even push the scope of assembly outside typical boundaries demanding truly creative solutions.
Flip Chip applications are a good example of this technology. Instances whereby placement tolerances push the limits of
conventional SMT equipment,but volumes and specialization preclude the use of stand alone die bonding equipment are
becoming more common.
In order to match the true requirements of the process to the capability of the machine,a determination of factors affecting
the accuracy must be made. Specified placement tolerances are vague and may not apply in all instances as stated.
The process development does not end with getting the devices placed,but extends into determining an adequate metrology
for verification of the placement accuracy. Applications where the placement tolerance is less than 25 microns create new
challenges for measurement. Additionally,imaging of these devices may prove to be the most challenging piece of the
development.
The application covered in this paper involves the placement of 2 Flip Chip devices end to end with tolerances of ± 10
microns. The body of the discussion will cover the challenges of the application and how these were addressed through the
partnership of the EMS and equipment manufacturer. Details will be given on the technical solutions for imaging,
movement,tooling and measurement as well as final process data.

With the combination of increased product complexity,increased frequencies and ever decreasing component sizes and
pitches designers are faced with the dilemma on how design their products in the most cost effective manner possible. In
larger more complex products designers most often than not are creating “islands of densities” or daughter cards that join
onto larger and more complex boards. In order for designers to “link” the daughter cards to the motherboard designers are
using newly designed interconnect products. Interconnect suppliers have introduced products such as a BGA type board to
board connector. Advantages of this type of connector extend into the contract manufacturing realm as the connectors are
processed during the mass reflow of the assembly eliminating process steps such as wave solder or press fit operations. The
manufacturability of these connectors have been evaluated and documented in earlier reports but little data is available on the
second level testing and reliability of these connectors. This report focuses on the manufacturability and reliability of the
interconnects generated from accelerated thermal cycling of the “Metropolis” test vehicle (connector test vehicle). The tests
were performed using IPC-9701 as a guideline. The “Metropolis” test vehicle is populated with two styles of a BGA
mezzanine connector,a BGA mounted socket and two press fit connectors.

This paper addresses the effect of pulse plating of electronic interconnects for advanced electronic modules. This paper
builds on earlier work by correlating plating cell and tank design issues and tank characterization studies with standard
mechanical and reliability tests. The current work evaluates the resulting copper deposits in terms of throwing power,
mechanical and reliability tests and compares the results to a current state-of-the-art process. The present work relies on
electrical mediation for a highly controlled electrodeposition process that results in a very uniform and reproducible deposit;
selection of the electric mediation parameters is based on considerations of mass transfer as well as microprofiles and
macroprofiles related to current distribution. Data for plating industry test panels containing PTHs of approximately 5:1,
10:1,and 15:1 aspect ratios are presented. Using a pulse waveform sequence,throwing powers of approximately 90-100%
are observed at plating rates of approximately 20 ASF.

Nanocrystalline and ultra-fine grain copper can potentially offer increased reliability and functionality of printed wiring
boards due to expected enhancements in strength and achievable wiring density by grain size reduction. In this research inhouse
synthesized nanocrystalline and ultra-fine grain-size copper foils produced by pulsed electrodeposition were compared
with commercially available electronic grade polycrystalline electrodeposited (EG-ED) and cold rolled annealed (EG-CRA)
copper foil. The microstructures of all materials were characterized by transmission electron microscopy (TEM). Nanoindentation
and the four-point probe technique were used to evaluate their hardness and electrical resistivity,respectively. It
is shown that grain size reduction results in significant increases in hardness at a moderate loss in conductivity.

Continuous measling,or unidirectional crazing,was observed in a multi-layer polyimide printed wiring board following
assembly operations. Damage to the PWB preferentially followed the warp direction of the glass fiber reinforcement and
extended beyond the region of localized heating. Further investigation revealed that glass fiber pullout in cross-sectional
mounts is an indicator of laminate material that is prone to measling or crazing. Testing showed that boards with fiber pullout
were significantly more likely to show damage in base material in subsequent process,especially when a drying bake was not
recently performed. Damage to these PWBs consisted of cracks not between bundles of glass-fiber reinforcement,but within
individual bundles. These cracks may produce reliability risks in PWB.