To meet future requirements for PWBs,various technologies of processes,materials and tools of PWBs have been discussed.
Especially important are technologies of circuit formation for high-end PWBs. Industrially the circuit formation method for
fine pattern has been changed,in these years,from the subtractive process to the Semi -Additive Process (SAP). SAP can
form finer circuits because it doesn’t cause side etching that is the problem of subtractive method. However the flash etching
process of SAP causes other problems such as short defects due to residual seed metal layer between circuits,circuit etching
and circuit delamination due to etching. Also,because of the roughness of the insulator surface that the circuits are formed
on,there are not only difficulties for fine circuits formation but loss of an electrical property.
In this paper,a new circuit formation method is discussed to overcome the problems that the flash etching process of SAP
causes. It does not need flash etching process therefore it can form finer patterns. The capability of this fine line circuit
formation depends upon the photo pattern resist resolution and was confirmed to perform well at L/S(Line/Space) = 10/10um
or less. Also the circuit pattern is buried in the insulator layer and is planer with the insulator surface,therefore the circuits
have high peel strength with insulator and there is less damage by manufacturing equipment or handling between processes.
This method is applicable to build up PCBs and FCPs as a circuit formation technology that meets future requirements.

Nowadays there are two major ways to achieve the conducting function of HDI Blind Hole One is to employ conducting
metal paste to fill in the blind holes after laser drilling. The other is to fill those mechanical drill holes by means of
conventional PTH technology. Referring to the second way,we discuss how to assess and assure the hole reliability in this
article using several methods of research,we try to demonstrate the relation between the reliability and some requirement
such as blind hole size,copper plating thickness,connecting area of pad in inner layer,under cut,and so on. We hope to
provide sufficient information for the design of blind holes and a set of reasonable design and manufacturing requirements.
When you call your family or friend for an urgent issue using your cell phone outdoors,if your cell phone suddenly does not
work suddenly,no voice,no signal,shut down automatically,and so on,it may cause you to hit the ceiling. This is
particularly true if you try again and the problem is same. Of course,the cell phone maker would rather not leave any bad
impressions in the eye of consumer,especially in the reliability of the phone’s performance.
Why a cell phone does not work suddenly has many reasons. As to the PCB,it may have a circuit connection problem. This is
particularly true in the case of blind holes for HDI that are not easy to find or test. In this article,we discuss the reliability of
blind holes that are formed on the outer layers with HDI technology as well as for those mechanical drilled holes produced by
means of conventional PTH technology. Applying several research techniques based on mass production conditions we will
determine which factors impact reliability and determine what are the reliable design parameter for blind holes that can insure
they can withstand a series of critical test conditions.

As more electronic assemblers move to lead free SMT production,concerns are raised over reflow cooling slopes and effects
on solder joints. Due to the higher peak temperatures,cooling slopes are naturally more aggressive if not controlled properly.
Impacts of variable cooling slopes should be considered for the transition to lead free assembly.
This paper evaluates the effect of variable cooling slopes on lead free solder joints. Controlled testing of lead free assemblies
subjected to various cooling slopes in both air and nitrogen environments is also discussed. Solder joints will be inspected for
solder joint grain structure under differing conditions of aggressive,medium,and mild cooling slopes. Data will be presented on the findings of this study along with suggestions of desirable cooling slopes and reflow system options to best support the
reflow cooling profile.

As lead free assembly is ramping up,wetting of lead free solder pastes is surfacing as the major paste performance tradeoff.
Global efforts to significantly increase lead free wetting chemically have proven unproductive to date. The “drop in” lead free
paste with respect to wetting looks to be improbable. This paper reports the findings of numerous studies using quantitative wetting gauges to measure solder paste wetting to the PCB surfaces. Wetting results with various lead free profiles,reflow
atmosphere oxygen concentrations and lead free PCB surface metallizations are compared and contrasted for their
contribution to maximizing lead free wetting. Although numerous lead free alloys are on the market today,this paper concentrates on the popular SAC (Sn/Ag/Cu) alloy specifically 95.5/4/0.5 in a no clean paste. In addition to wetting,solder
defects and voiding are included in the comparisons to reveal the best overall lead free reflow process.

Traditional reflow profiles for lead-free soldering typically require longer processing times due to elevated peak temperatures
and flux activation times defined by solder paste suppliers. These profiles become particularly challenging when a wide
variety of packaging types are integrated within a single circuit design. Further difficulty is presented when product designs
with high thermal mass,such as heat slugs and metal substrates,are processed. These designs create large thermal gradients
throughout a circuit assembly and add further complexity to finding an “optimal” profile window. All of these issues create a
significant increase in reflow processing times for lead-free soldering.
This paper investigates these increased processing times required for high volume manufacturing of lead-free electronics. A
study of typical process capacity and real throughput capacity is presented. The study evaluates high volume electronics
manufacturing ranging from small circuit assemblies (e.g. cell phone) to large circuit assemblies (e.g. automotive and
computers) and investigates a series of “best” reflow profiles to accelerate the standard lead-free process window to meet a
targeted manufacturing capacity using an automated profiling system. A test vehicle is then fabricated using this defined
process window and tested for quality (solder voiding and appearance) and solder joint reliability (accelerated life testing).
The designed test vehicle includes components from a large physical distribution including: small and large BGAs,QFNs,
and any type discrete components. During assembly,virtual profiling is used to document any deviations to the process
profile window. The quality and reliability data are presented within this publication and failure analysis is included to
determine the capability of this proposed profile.
When employed,this profiling strategy allows many manufacturers to reduce the processing time for reflowing lead-free
circuit assemblies without significant lost in manufacturing quality or reliability. Furthermore,this study provides a sound
understanding and limitations for using accelerated profiling speeds for lead-free soldering applications.

The copper plating process is one of the most critical steps in the high end PCB manufacturing process. Although the
deposition inside through holes and blind holes is the key factor for reducing the fall out fraction,the thickness distribution
over the entire layout is also critical,in particular for multiplayer designs. A performance plating simulation tool (P2ST) for
the prediction of layer thickness distributions over PCB's is presented. This tool takes into account the bath characteristics
(conductivity,electrode polarization),the PCB layout,the electrical signal parameters (DC current or bipolar current
amplitudes and duty cycle),and the PCB positioning in the plating tank.
This tool allows us to perform a fast prediction of the layer thickness distribution over tracks,pads,ground planes,robbers
etc. The tool can be used by any PCB manufacturer either in the cost estimation phase and/or as an auxiliary tool in the CAM
work flow. In the latter case,the tools represents a powerful asset for the optimization of pulse signal and/or background
patters (copper balancing) towards layer uniformity specifications.

Horizontal and vertical pulse plating have been widely used for panel plating in PCB industry,but rarely used for pattern
plating. This article analyzes and reviews the crystal structure,throwing power,surface distribution,elongation,appearance,
thermal shock,temperature cycling and IST test of copper plating after pattern plating. The article also describes some
problems and their resolution in production.

Two important aspects concerning optimum performance of a (reverse) pulse plating line are (i) the uniform and correct pulse
shapes anywhere on the PCB and (ii) the uniformity of the plating current density (thickness distribution) over the whole
plating window of a vertical line or the entire width of a PCB in a horizontal line. To measure both precisely,comfortably,
and quickly the island method was enhanced to Optipulse 80. Special test boards with measurement islands and calibrated
shunts on both sides are used to check site-specifically the cathodic plating current density as close as possible to production
conditions. Sampling frequencies up to 20 kHz precisely resolve pulses as short as 0.5 ms. Up to 80 channels are sufficient to
obtain a well resolved overview over the plating window of most vertical lines within less than ten minutes. Statistical data
evaluation and visualization features make this a powerful tool for optimization of pulse plating lines (also applicable to DC
plating,of course). The system now has been successfully in use for more than three years. This paper presents a short review
of its history and the actual features as well as some examples from recent data.

The upcoming European Union RoHS and WEEE directives are driving new requirements for the management and exchange
of information,both across the extended electronics manufacturing value chain,and across the product lifecycle. The
Restriction of Certain Hazardous Substances in electrical and electronic equipment (RoHS) bans or severely restricts the use
of certain substances in the manufacture and assembly of electronics products to be marketed in the EU. The regulation of
Waste from Electrical and Electronic Equipment (WEEE) places strict requirements on the handling and disposition of
electronic products at their end of life. All electronics OEMs that sell products into the EU states will have to comply or they
will lose access to these markets. Information on the material composition of all components and bulk materials that go into
the manufacturing of products will have to be available and shared,across multiple tiers of the supply chain,to support RoHS
compliance. Information on substances of concern and the location of any hazardous substances,along with disassembly
instructions,will have to be available to recyclers to support WEEE. Additional information will likely be required to support
the upcoming directive on Design for Energy Using Products. Some estimates1 place the cost of enhancing and updating IT
systems to support environmental compliance for an average electronics producer at $2-$3 million over the next 3 years.

System in package (SiP) technology has grown significantly in the past several years. It was barely mentioned in the National
Electronics Manufacturing Initiative’s (NEMI’s) 2000 roadmap,but by the 2002 roadmap,SiP was one of the fastest growing
packaging technologies. Even though,at that time,SiP represented a relatively small percentage of the total unit volume,the
2002 NEMI roadmap noted that SIP was becoming a common technology in the high-growth Bluetooth,WLAN (wireless
local area network) and mobile phone applications. By 2004,SiP had grown so significantly that it was added to the roadmap
as a new product emulator group (one of seven),which are used to define future manufacturing needs across the entire
electronics supply chain.