Eutectic Bi-42Sn solder is a low melting point alternative to lead-based solders,particularly for low cost,consumer electronics. In earlier work,the mechanical properties of this solder have been enhanced by small additions of silver (0.5%-3%). In this study,Bi-42Sn-1Ag solder paste was used to assemble lead-free PBGAs (Sn-0.7Cu,Sn-3.5Ag,and Sn-3.5Ag-0.7Cu ball compositions) on lead-free PCB surfaces (organic solderability preservative (OSP),electroless nickel/immersion gold,and immersion tin). These lead-free assemblies exhibit accelerated thermal cycling (ATC) performance comparable to the performance of assemblies made with Sn-37Pb,surviving 7000 cycles (40 min. cycles between –25?C and 75?C). In addition,with sufficient solder paste these lead-free assemblies have bend strengths approximately equal to the strength of a comparable Sn-37Pb assembly. Moreover,bend failure occurs between the FR-4 and the inlaid copper pad for both solders. To understand the reliability and mechanical behavior,cross-sections of solder joints were evaluated.

This paper will discuss the implementation of real-time automated SPC for the Reflow Process. Topics covered will include: a new statistical method for quantifying the thermal process performance; methods for ensuring that SPC data provides a true representation of process capability; and the value of automated real-time SPC. To realize the full benefit of an SPC program,it is essential to define and set process specific control limits. SPC programs based on “targets” rather than process specific control limits are not capable of reliably predicting process trends,which is the primary function of an SPC program. Developing a fully functional SPC program requires a sufficient data set on which to project process trends. Another key factor in the success of an SPC program is efficiency. An inefficient method of data gathering and analysis is a guarantee of failure,as a program that consumes excess resources will quickly be abandoned. One method for increasing SPC program efficiency is to focus on key process statistics. A statistical method has been developed that reduces all key process statistics to a single number: the Process Window Index. The calculation of the process Window Index will be defined and its validity as a statistical method for developing Cp and Cpk for the reflow process established. The continuous and automated gathering of data is essential for successful SPC monitoring of the reflow process. Current methods generally rely on periodic profiling,which disrupts production and provides an inaccurate “picture” of the process. Automated Continuous Monitoring Systems for the reflow process have been developed. These systems can provide a data point for every board processed by calculating a “Virtual Profile”. A design of experiment (DOE) will be run to establish that the “Virtual Profile” is a reliable method of continuously gathering data on the reflow process. Experiment methods and results will be included. Automated SPC for the reflow process offers significant benefits for Electronics Assemblers. Automated SPC provides a significant sales tool for EMS’s,as it allows them to prove to customers that their reflow process is in control and that their facility is dedicated to quality electronics assembly. This paper will be of interest to engineers and managers interested in increasing reflow process efficiency and quality.

Wafer-applied underfills are key to the widespread acceptance of flip chip technology. This NIST-ATP funded consortium is developing the materials and processes for achieving a wafer-applied underfill system that is both self-fluxing and reworkable. In the present work,the factors impacting successful assembly of pre-underfilled chips are studied. Flip chips with the underfill material pre-applied to the devices were assembled in the lab using production equipment. The presence of the underfill coating was examined for its influence on vision recognition,placement and reflow.

Flip Chip on Board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases,assembly processes are not capable of providing the high throughputs needed for integrated Surface Mount Technology (SMT) processing.1 A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface.2 This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages,reflow profile parameter effects on eutectic solder wetting of high lead solder bumps,interactions between the no-flow underfill materials and the package solder interconnect and tented via features,void capture and void formation during processing,and material set compatibility and the effects on long term reliability performance.

Automated Optical Inspection (AOI) equipment has become an option for electronics manufacturers who are considering how to improve performance on the production line. During the last few years rapid changes have occurred in mounting technology for PCB assemblies. At the same time that equipment has changed in order to be able to build to the new market requirements,new techniques are needed to test/inspect those new products.

The latest types of components launched by the leading component manufacturers have increased the need for process control in rework. These packages are referred to by the generic name Land Grid Array (LGA) or the specific package names Leadless Leadframe Package (LLP) and Micro Lead Frame (MLF). These packages are unique because they contain multiple pad sizes and shapes on the same device. They are also soldered with all terminations on the underside of the package,similar to BGA. These components lend themselves to normal assembly techniques such as screen-printing the PCB,automatic pick and place,then convection reflow. The LLP design has a large center pad that is often soldered to PCB as a ground or power connection. The soldered center pads can also act as a heat spreader to the PCB substrate. This helps keep the part cool and controls expansion of the part to the substrate so that the TCE (Thermal coefficients of expansion) tolerances of the part to the PCB board material are minimized. The rework process for LLPs requires all the pads to be soldered to the same height or the potential for small land connections could be an issue. The solder paste volume used for the center and array pads must be controlled to achieve good,reliable joints.

As imaging requirements continue to move towards finer resolution,accurate layer-to-layer alignment becomes an increasingly important factor that influences product yield. One of the major contributors to yield loss in fine-line products is the dimensional instability of the substrate. Large rigid substrates as well as flexible films often undergo
slight dimensional changes as a result of the different PWB manufacturing process steps. In addition,the changes in the substrate dimensions are often non-isotropic. Manufacturers have been compensating for this problem by measuring the changes in the substrate and plotting new artwork that is matched to the dimensions of the processed substrate. This time-consuming and costly manufacturing practice can be eliminated through the use of the new
Anamorphic X-Y Scaling technology that enables independent magnification compensation in two dimensions for laser projection exposures. In this paper,we present the results of studies conducted on laser projection imaging equipment and specifically review the performance of the X-Y scaling capability.

New vertical continuous plating equipment has been developed while taking into consideration production and environmental requirements. The vertical continuous plating equipment conveys printed circuit boards continuously without using any racks and carries out high quality plating. This paper discloses an outline and features of our
newly developed vertical continuous plating equipment for printed circuit boards,and various data such as surface deposited thickness distribution and throwing power on the through hole and blind via holes (BVH).

Permittivity and dissipation factor (Dk and Df) are effects of polarization of different components of the dielectric substrate material when subjected to an electrical field. Reliable design of PDAs to be used at very low temperature (-5 °C) and very high temperature (60 °C) with different amounts of humidity,require knowledge of range of Dk and
Df within this domain. A database of these important design parameters for PWBs,has been developed for THERMOUNT® RT materials. Effects of variations in the level of moisture (bone dry to completely saturated at various relative humidity levels),testing temperature (-5 °C to 60°C) and testing frequencies (500 MHz to 1.5 GHz) on Dk and Df are reported. A very reliable design of PWB can be accomplished with this database.

Using conventional PWB copper electroplating techniques (DC bath chemistry with air agitation),non-uniform deposition inside blind via features may arise when the vias have diameters less than 6 mils and aspect ratios greater than one. These observations result from two main causes: unfavorable solution hydrodynamics and the presence of air bubbles. Ultrasonic agitation (UA),well known for cleaning purposes,can provide a strong local agitation that "refreshes" the plating solution inside holes together with punching small trapped air bubbles. It has been demonstrated that UA greatly enhances the throwing power inside small blind via features. It must be pointed out that low UA power densities were used (2 to 8 W.gal-1). The frequency was 40 kHz and air was bubbled during plating. Using a conventional DC plating solution at 15 ASF,throwing power was improved on average by 35.9 %
for vias having a diameter of 6 mils and aspect ratio between 1.25 and 1.5. A more drastic 74.6 % throwing power improvement was noted for 4 mils blind vias having an aspect ratio of 1.9 and 2.4. Through ductility measurements,it has been also demonstrated that plated through hole reliability was improved using mild UA.