Today’s HDI field of technology is coming under more and more pressure to increase wiring density and,even more
importantly,to decrease manufacturing costs. The current technological approach does not permit an adequate response to
this challenge and thus new,disruptive manufacturing technologies have to be developed.
Imprinting as a means of forming conductor patterns as well as via holes has been under discussion for several years now. A
more crucial issue,however,is to find a method for filling the recessed features reliably and inclusion-free with solid copper,
and consequently the overall build-up concept has to be adapted in order to utilize the full potential of this novel technique.
This paper describes a new manufacturing approach based on imprinting,a special copper plating process,followed by an
etch-back step. This method is capable of producing lines and spaces down to 10µm and thicknesses of up to 40µm.
Conductor and via pattern are produced simultaneously,thus making padless designs feasible.
The key elements of this radical new approach are the manufacture of the imprinting stamp,the imprinting itself and the
copper filling. Each necessary process step has been verified in a lab environment,and first functional samples have been
successfully produced. Continuing further development is underway to bring this technology from lab to fab within a
reasonable timeframe.

JPCA has been developing standards necessary for adoption of optoelectronic technology especially for consumer
applications for years. The subjects being drafted are the technology that is fairly matured and actually used in some
applications in the industry. JPCA has identified some seventy items for standardization and published seven
documents as the first set of documents in June 2003. Another dozen documents will be released in the spring of
2004. IPC-0040 has been just published and is an excellent guideline for optoelectronic assembly technology we
need. It is our hope that the documents developed by JPCA will be a part of the documents to be developed based
on the recommendation made in IPC-0040. We expect our effort will encourage people in the industry to
incorporate OE technology in their design of new products,not only in the area of telecommunications but rather in
the areas of consumer applications and information processing including but not limited to computers,game
machines and others.

Reliable copper interconnects are a primary requirement for most printed wiring board applications. A variety of
wet manufacturing processes play an important role in the formation of durable interconnects,including plated thru
hole (PTH) metallization with electroless copper/electrolytic copper plate. PTH interplane (IP) separation may
become an issue when cleanliness and texturing of the IP before electroless deposition is not optimal. Smear
removal pretreatment and subsequent processing to provide a clean and properly textured IP before electroless
deposition have a strong influence on the resulting roughness and chemical content of the outermost layer of copper
surfaces. A method by which to evaluate the surface state of copper during each preclean and chemical processing
step would be beneficial to understanding copper surface chemistry,and consequently,some of the origins of IP
separation.
The tendency for a metal surface such as copper to undergo electrochemical corrosion can provide some qualitative,
as well as limited quantitative information on the relative state of the copper surface after exposure to various
corrosive solutions. For example,copper precleaning solutions,including permanganate desmear and acid
conditioning,are inherently corrosive and are required in order to generate a properly textured clean surface free of
contaminates upon which electroless copper can successfully adhere. The relative corrosivity of the solution the
copper is exposed to during preclean will ultimately affect the corrosion rate or corrosion resistance of the surface
when exposed to yet another corrosive electrolyte. For example,a relatively corrosive preclean step such as sodium
persulfate microetch may leave the copper surface in a more rough,oxidized state than a simple acidified rinse.
Consequently,it could be expected that the corrosion rate of this oxidized copper surface would be relatively low in
comparison to the corrosion rate of a smooth,pure copper surface afforded by a gentler acid rinse. Because IP
separation is a manifestation of poor adhesion between the base copper/ electroless copper or the electroless
copper/electrolytic copper interface,a more detailed investigation of the chemical factors that cause changes in
copper surfaces can be helpful in understanding the underlying cause(s).
With this objective in mind,a copper clad test vehicle was subjected to desmear and electroless copper plate along
with the associated precleans,with a portion of it removed,rinsed and dried after exposure to each individual
chemical processing step. The corrosion behavior of each resulting sample surface was electrochemically studied by
generating Tafel plots of each surface in 0.3% NaCl electrolyte. Corrosion rates of each unique copper surface after
various wet process steps and the corrosion potential of each surface in electrolyte are reported.

Two years ago when IBM Endicott,now Endicott Interconnect (EI),was preparing to install a new Acid Copper
plating system,the Periodic Reverse Pulse (PRP) tanks installed at the end of the line were seen as a current density
capacity enhancement for "standard thickness" boards. At the time,there was limited demand for thicker,higher
aspect ratio boards which required plating in the pulse tanks. A lot has changed in the last two years!
In 2001,electroplated boards with a 15:1 aspect ratio were on EI’s strategic road map; now they are on the
manufacturing floor. The pulse tanks,empty two years ago,have evolved from merely being a productivity
enhancement to becoming technology enablers - plating EI’s highest aspect ratio boards.
This paper will discuss some of the methodologies of the plating system’s design,the strategy deployed in
evaluating and qualifying PRP and the migration to thicker boards. All of EI’s PRP work on the production line has
been done with Atotech's CUPRAPULSE S4 LEVELER system and PE PRP/DC rectifiers,capable of +1200A / -
3600A; but the methodology and results should be applicable for most plating systems. The impact of process
parameters and board features play a major role,but central to our findings is the need to migrate from a "one bath
for all applications" mentality,which compromises results and capability. One simply cannot get optimal results by
merely reducing the current density of their existing bath and just hoping for the best.

The Cray X1™ system dramatically extends the capability of supercomputers with High efficiency and extreme
performance. Specifically designed to meet the needs of the high-end user,the Cray X1 provides exceptional
memory bandwidth,low-latency interconnects and vector-processing capabilities.
While development of the Cray X1 received substantial support from several U.S. government agencies,including
the National Security Agency (NSA),Cray decided to develop its own specifications for printed wiring boards,
materials and reliability.
This paper will discuss the introduction of the Newest Cray X1 Supercomputer,and the requirements of the printed
wiring boards used in the systems. It will also focus on the Unique Challenges of the fabrication of the PWB,the
different materials explored,their properties,and their setbacks. Also addressed will be the stringent electrical test
requirements and the many quality and reliability controls for PCB acceptance from its suppliers.

Design of printed wiring boards allowing devices to function at increasing signal transmission rates is a difficult task. As
operating frequencies increase beyond one Gigahertz the availability and accuracy of Dielectric Constant and Dissipation
Factor data for PWB substrates becomes very limited. To improve the availability of dielectric data on PWB substrates,
Cookson Electronics PWB Materials and Chemistry Sector worked with the Electronics Manufacturing Technology Branch
of NAVSEA to develop reliable test capabilities and evaluate various substrates. The test technique utilized the “Waveguide
Slab” method (1) to measure the Dielectric Constant and Dissipation Factors of various substrate materials between 4 and 18
GHz. Results of the testing of these substrates will be presented. Substrates tested include FR-4,Thermally Stable Epoxy,
Aramid reinforce epoxy,halogen free,Polyimide,BT,and other low DK/low DF materials. Information about the testing
procedure and accuracy will also be discussed.

This paper addresses the growing need in the Printed Wiring Board industry to measure and test propagation delay
parameters of board interconnects within the fabrication process. The state of current art is detailed in discussions of four
different methods of measurement including their respective advantages and disadvantages. Definitions and basic
considerations for the measurement process are also discussed. The conclusion is that accurate and repeatable measurements
of propagation delay in the manufacturing environment can be made with existing equipment technology and with a best
known method.

Designing a signal path to provide a particular impedance is thought to be a well understood science. The first issue which is
often overlooked is to analytically establish the need for specifying a controlled impedance signal path. After determining
this to be the case,the designer normally selects a combination of line width and dielectric thickness to satisfy the stated
requirement. There are usually,however,an infinity of selections that will satisfy any stated impedance requirement.
Obviously,one would prefer to select the combination that will minimize variations in the impedance caused by the
fabrication process. This becomes extremely important in designs using low impedance paths such as Rambus.
This paper discusses an analytical procedure addressing these issues. Once the optimal selection is made,it is then possible as
further described in this paper,to define the statistical variation of the impedance to be expected for the optimal construction.

Abstract
Electroplated tin and tin alloy coatings are used in electronics plating applications as a solderable and corrosion resistant
surface finish for components and printed circuit boards (PCBs). Though applications vary,there are some commonalities
regarding the requirements for this final surface coating. One issue is long term solderability performance,defined as the
ability of the surface finish to wet with solder and form a reliable solder joint to the next-level substrate without defects
that would impair the electrical or mechanical interconnection.
There are many factors that determine solderability performance of an electroplated coating,surface oxide formation being
foremost among them. The rate of formation of the surface oxide depends on the temperature and time of the thermal
excursion the component or PCB is exposed to - the higher the temperature and longer the time,the thicker the surface
oxide that is formed. To ensure the highest degree of solderability,it is important to prevent or minimize exposure of the
tin plated surface to elevated temperatures for extended periods of time.
In terms of production implementation,this is often very difficult to achieve because the type and duration of thermal
excursions is dictated by post-plating processing conditions and/or end-user specifications. For example,in the case of Pbfree
component pure tin plating,many end-users have begun to specify that a “stress relief bake” (SRB) of typically 150°C
for one hour be implemented to reduce compressive stresses in the deposit to minimize long term whisker growth
propensity of the deposit. After the SRB,the component still has to pass end-user solderability testing requirements which
typically involve additional heat and humidity conditioning. Inevitably,this causes thicker surface oxides to form,which
in turn reduces the solderability performance of the tin or tin alloy deposit and indeed today in current semiconductor Pbfree
component processing,it is very difficult to pass the most stringent end-user solderability test requirements after
implementation of the newly required SRB. Therefore it would be highly desirable to find a way to prevent or minimize
surface oxide formation on such deposits.
This paper will introduce a new patent-pending technology which minimizes oxidation of tin and tin alloy coatings
through implementation of a proprietary additive in the electroplating bath. Results in terms of demonstrating reduction of
surface oxide formation resulting from this technology as well as improvements in solderability performance from both
laboratory studies and production will be presented.

For decades,tin-lead has been used as the primary surface finish for compliant pins and plated through holes (PTH) of
printed circuit board (PCB) in press-fit connections. Therefore,most test results on press-fit performance are focused on the
tin-lead finishes for the connections. Due to the discontinuation of the use of lead in electric and electronic components,the
trend of using lead-free manufacturing for PCB’s and connectors is being vigorously pursued by the industry. The present
study is intended to evaluate press-fit connections using various lead-free finishes on compliant pins and PTH’s and then
compare to tin-lead finish. The lead-free finishes for the compliant pins are plated with matte and bright pure tin,and the
lead-free finishes for the PTH’s are electroplated Au,OSP,and immersion tin,Au,and Ag finishes.
In the design of experiments (DOE) of the current study,single pin tests were used to obtain the DOE outputs of insertion
and retention forces for eye-of-the-needle (EON) compliant pins in PTH’s. For all three EON finishes (two pure tin and one
tin-lead),the DOE results show that finished PTH size is the most important factor to determine the insertion force. The
insertion force is a strong inverted linear function of finished PTH size (i.e.,a larger force is required for a smaller finished
PTH size). The impact from pin installation/repair cycle is the second factor behind the finished PTH size. The finishes of
EON and PTH are only minor factors for the insertion force. In contrast to the insertion force,the retention force is rather flat
regarding the finished PTH size. The DOE results also indicate the EON finish is ranked as the number one factor to affect
the retention force. The matte tin EON pin produces higher retention force than the tin-lead finish. The EON of bright tin
finish produces a slightly lower retention force than the tin-lead. Within the five lead-free and one tin-lead finishes for the
PTH’s in the study,the lead-free finishes of OSP,immersion Au and electroplated Au provide retention forces in the lower
end,and the immersion tin always provides the highest retention force. However,each of these combinations results in stable
electrical performance and a reliable connection.