Chip Scale Package (CSP) technology is growing at a rapid pace since its emergence in the electronics
manufacturing industry. As the solder joint size decreases,it has become apparent that underfill is necessary to meet
certain reliability standards with CSPs,specifically drop testing. The need to underfill the CSP package has exerted
the same drawbacks that are involved in flip chip assembly. No-flow underfills pose potential in this area as they can
be incorporated into the standard SMT process with no post reflow processing. Most new materials simultaneously
reflow and cure in the same reflow process used for standard SMT solder pastes. This work presents a reliability
study of several commercial no-flow underfills and compares these CSPs to CSPs assembled without underfill and
CSPs assembled with conventional fast-flow,snap-cure underfills. Samples were built using solder paste only,flux
only,combinations of conventional underfill and solder paste or flux,and no-flow underfills. The reliability tests
include liquid-to-liquid thermal shock (-40oC to 125oC) and board level drop tests (6-feet). Samples assembled with
underfilled were benchmarked against the samples that were not underfilled. The CSP test vehicles consisted of a
printed circuit board with 10 CSPs having 84 I/O and a 0.5-mm pitch. Through these tests,it has been determined
that no-flow underfills can pass over 1000 cycles in liquid-liquid thermal shock,the typical standard for
package/product qualification. Samples assembled with no-flow underfills also exhibited an increase in reliability
during drop testing as compared to non-underfilled samples. The reliability data shows that no-flow underfill
implementation on CSP increases reliability as compared to non-underfilled samples.

Underfill technology has been used to minimize the mismatch of the Coefficient of Thermal Expansion (CTE)
in flip chip technology. An extension of this application has been used to increase the mechanical strength of
Chip Scale Packages (CSPs).
This paper will discuss the impact of non-reworkable and reworkable underfill,and corner-bonding on the mechanical
strength of CSPs. Reliability tests performed include drop,shear,bending and thermal shock tests. The
goal is to understand the reliability and degree of protection each of these underfill material offers.

The trend in optical communications is toward all-optical Networks,which transmit,manage and route traffic over
extended distances in the optical domain,without the need for power-hungry and bandwidth-limiting electronic
switching equipment. The Design & Technology Center at Solectron in Bordeaux has reached a trade agreement
with a start-up company for the entire development of new optical switches. This start-up develops an original
switch technology which is based on the thermo-optic effect. The Design & Technology Center has taken up the
challenge for the entire packaging developments. These developments take into account the design and assembly of
the electronic cards,the mechanical housing,and the interconnection of the optical switch,consisting of a 5” inches
silicon wafer with a pigtailed optical fiber ribbon. All the engineering teams of the Design & Technology Center
have contributed to these developments. The purpose of this paper is to review the integration of a silicon wafer
inside a package using the wire bonding technique. In a first part,the packaging problematic is presented and more
specifically the packaging for optical devices. Then the baseline process is reviewed with emphasis on Flexible PCB
design & manufacturing,wire bonding and encapsulation processes.

The outgassing level of materials (such as adhesives,composites,plastics,etc.) that are used to assemble and
construct optoelectronic packages,sub-assemblies,and other electronic materials is becoming more of a necessary
design variable. The standard methodology to measure outgassing levels within electronics manufacturing utilizes
the NASA ASTM E-595 method,which generates only two numbers: total mass loss (TML) and collected volatile
condensable materials (CVCM). The downside to this methodology is that it cannot be modified to meet the realworld
operation conditions of the assembly nor can it tell you the identity of the outgassing compounds. Often,
being able to identify what is outgassing is much more important than the total volume of outgassing. This
presentation will present a description and various applications of the dynamic headspace (DHS) outgassing
analytical methodology that can study any material,in any construction,at any temperature,at sub-nanogram levels,
with complete compound quantitation and identification. The analytical system consists of an outgassing manifold
followed by gas chromatography with mass spectral detection. This technique is based upon testing required by all
Tier I and Tier II OEM suppliers within the hard disk drive industry.

Electronic devices become more and more smaller. Electronic assemblies are sensitive against electrostatic discharge
just as much as its smallest and most sensitive element. So protection systems are necessary in all areas,where these
devices and assemblies are handled and used. Sometimes it seems to us,that steps are not any more necessary. But
the last time showed us,that every time new sources for electrostatic charge can be developed,which have not been
imagined until now. A person can be equipped ESD - required very good,but the whole environs of the proceeding
is a danger,which become bigger and bigger. Especially the activities,which are made automatically,cause big
damages at the devices and assemblies. In the first part necessary steps are described,which are needed to equip
persons and working places. The second part deals with machines and assemblies. Especially there the most
problems come out. In the last part an overview is given about the necessary test methods.

Sandia National Laboratories has programs covering
the range of MEMS technologies from LIGA to bulk
to surface micromachining. These MEMS
technologies are being considered for an equally
broad range of applications,including sensors,
actuators,optics,and microfluidics. As these
technologies have moved from the research to the
prototype product stage,packaging has been required
to develop new capabilities to integrated MEMS and
other technologies into functional microsystems. This
paper discusses several MEMS packaging efforts,
focusing mainly on inserting the SUMMiT™ V
(referred to hereafter as 5-level polysilicon) surface
micromachining technology into fieldable
Microsystems.
Sandia National Laboratories is engaged in a broad
range of MEMS and MEMS-based microsystems
development. This ranges from basic research on
materials,processes,and reliability,to development
of microsystems to meet the national security needs
of our customers. Packaging is crucial to fielding real
Microsystems throughout the industry. Packaging is
also critical to the basic research as well,since the
available environments in a package provide bounds
on materials,processes,and certainly reliability. This
paper will discuss several areas of packaging research
and development at Sandia.

One of the greatest obstacles in commercialization of MEMS is the cost of packaging and assembly. Packaging
needs for MicroSystems and MEMS technology vary by structure and application. Major improvements in MEMs
packaging technology are required to enable the growth of the MEMS market. This paper examines some of the
issues and challenges in packaging and assembly for a variety of devices.

A new type of Micro-Electro-Mechanical System (MEMS) structure has been developed on a printed wiring board
(PWB) platform. PWB,embedded passives (EP) and High Density Interconnect (HDI) technologies were utilized to
fabricate these structures in processes analogous to silicon MEMS. A microfluidic device has been successfully
demonstrated using these technologies. The system includes heaters,microchannels and valves,which could be
stand alone components or be combined with other plastic components. These components are amenable to further
integration for low cost microfluidic modules and systems for biological and chemical sensing applications.

The full hermetic package for electronics and
optoelectronic (OE) devices was first developed in
the 1800’s and has served these industries well. The
earliest optoelectronic devices,cathode ray tubes
(CRT) demonstrated in the late 1800’s,used a sealed
glass vacuum enclosure. The Braun Tube,for
example,was a scanning CRT display system that
used a glass envelope to seal out the atmosphere and
maintain the required vacuum. Later,electronic
vacuum tubes were developed,starting with the
Fleming diode that also used a glass envelope. A few
years later,De Forest introduced the triode (Audion)
that was able to amplify,making it the first active
electronic device. Many of the early OE and
electronic devices required a vacuum to operate
because the flow of electrons through free space was
part of the mechanism. Today,only a small minority
of products requires a vacuum. Yet,the century-old
tradition of the full-hermetic sealed enclosure has
continued for many products. Figure 1 shows an early
hermetic package used for one of the first electronic
devices.

With the Waste Electrical and Electronic Equipment
(WEEE) Directive in Europe outlawing lead from
many electronic devices produced and imported in
the EU by July 2006,as well as with foreign
competition driving the implementation of lead-free
electronics assembly around the world,it appears that
the drive towards lead-free electronic assembly may
be inevitable. However,even with years of lead-free
research already behind us,additional questions
regarding how manufacturers can successfully
transition to lead-free assembly continue to arise.
To successfully achieve lead-free electronics
assembly,each participant in the manufacturing
process,from purchasing to engineering to
maintenance to quality,must have a solid
understanding of the changes required of them. This
pertains to considerations regarding design,
components,PWBs,solder alloys,fluxes,printing,
reflow,wave soldering,rework,cleaning,equipment
wear & tear and inspection. Engineering personnel in
particular will have to pay close attention to design,
components,PWBs,solder alloys,fluxes,and the
printing,reflow,wave soldering,rework,cleaning,
equipment and inspection processes.