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We have developed a new thermosetting polyimide build-up material for high performance build-up PWBs,which can mount
high speed CPUs with high I/O numbers. These PWBs meet the following requirements; good processability for the
fine-pitched circuits,the low dielectric characteristics,and the excellent mechanical properties.
Our proposed polyimide build-up material shows a dielectric constant (Dk) of 3.1 and a dielectric loss (Df) of 0.01 (at 1GHz).
Moreover the material shows following mechanical properties; a low coefficient of thermal expansion (CTE) of 45ppm and a
tensile strength of 100MPa. Even though the material has a low surface roughness Ra of less than 200n meters,we have
successfully deposited an electro-less plated copper layer with very high peel strength. This means that the material is
suitable for fabricating fine-pitched circuits,even when using a conventional semi-additive process. Actually,we could make
a fine-pitched circuit of less than 10micron L/S (Line and Space).

As a promising candidate for future substrate with high pin-count and low transmission loss at high frequency,we have
developed an all polyimide multi-layered board laminated by single batch process. Compared with circuit boards of glassepoxy
and ceramics,this circuit board made from polyimide films is thin and decreases transmission loss. It makes wiringdensity
higher and manufacturing cost lower,because of having all-layer IVH,Inner Via Hole,structure fabricated by single
batch process. It is a significant feature that the process applies new interconnection technology to formation of conductive
paste via in polyimide films,by laser-drilling and screen printing. By the most suitable condition of paste volume,
temperature and pressure in laminating process,we have achieved 1.0 milli-ohms in resistance for each via.

A Design of Experiment (DOE) was conducted to determine the best filler,or combination of fillers that would offer the best
reduction of CTE expansion from 50oC to 260o C without compromising electrical,chemical,mechanical or thermal
performance of the base Polyimide resin. Our study here shows that a unique combination of fillers can reduce the percent zaxis
expansion of a V0 Polyimide from 1.45% total expansion to 1.28% better than any single type of filler. Thus offering
higher reliability in Printed Wiring Board (PWB) applications that continuously operate in conditions of severe thermal
cycling.

This newly developed material and process enable the manufacturing,using a single pressing process,of multi-layer circuit
boards with inner via-holes in every layer. Because this material utilizes conventional circuit board materials for its structural
components,it not only provides proven high reliability and ease of circuit assembly,but also offers a short lead-time and high
production yield due to adoption of the following processes used during the manufacture of conventional printed circuit boards.
§ Use of a mu lti-layer substrate consisting of copper foil,glass-cloth-based insulation layer,adhesive layer,and cover film
§ Application of an etching process to the copper foil to produce a fine-patterned circuit
§ Generation of blind via -holes using laser processing and hole cleaning
§ Formation of via-bumps by filling metal-based paste and removing the cover film
§ A multi-layer circuit board with inner via-holes in all layers can be produced by aligning the insulation layers and pressing
them together in a single operation.
The materials used in this process require a variety of key technologies that enable laser processing,dimensional control,
conductive paste filling etc. This paper describes these techniques and includes an example of the production of a multi-layer
circuit board in a single pressing operation,followed by reliability evaluation results for the whole circuit board.

The trends of increased functionality and reduced size of portable wireless products,such as handsets; PDAs are demanding
increased routing densities for printed circuit boards. The handheld wireless product market place demands products that are
small,thin,low-cost and lightweight and improved user interfaces. In addition,the convergence of handheld wireless phones
with palmtop computers and Internet appliances is accelerating the need for functional circuits designed with smallest,lowcost
technology.
Historically,the industry has met this challenge through high density interconnect technology and increased silicon
integration and component miniaturization. Microvia high density interconnect (HDI) also known as build up technology,is
one method for constructing circuit boards with high routing density demands.1
For HDI board,vias can be formed using unreinforced dielectric such as Resin Coated Foil (RCF),using processing
techniques such as laser drilling or photoimaging. The vias are then metallized using electroless copper/electrolytic plating.
The advantage of the HDI construction is the ability to create smaller vias (6 mils) and via pad sizes. This enables higher
routing density,lower metal count,reduced board area and increased functionality as compared to conventional boards. HDI
improves the wiring density by using build up microvias in the outer layers. However there is still dead space where
components cannot be mounted and lines cannot be wired,because of staggered via hole structure.
On the other hand,ALIVH-G (Any Layer Interstitial via Hole) needs no through hole. This is because any two layers are
electrically connected by IVH (Interstitial via Hole). The IVH can be placed in any position. Since there is no through hole
that disturbs interconnections between components,the dead space becomes reduced and the wiring capability is improved
greatly.2
Past board technologies used stacked microvias on the outer layers. Current board designs use ALIVH-G technology. These
vias are laser drilled and the interconnection technology used is conductive copper paste. The typical design rule is
Lines/Space 100/100 micron and Via /Land is 200/400 microns. ALIVH-G technology makes a lightweight substrate (less
than 100g)
The paper presents the evaluation conducted to ensure the stability of the laminate and microvias through the double sided
reflow process. This was evaluated as a part of the phone product qualification build.

In recent years,along with the further progress of network systems,mobile communication systems and high performance
servers printed wiring boards (PWBs),which are key components in these products,are increasing in importance,and are
required for technology innovation.
Especially,the substrates in the field of high-end ASICs require more high density and high performance,and CSP and
Module substrates in the field of mobile application require more high density and downsizing. The demands for the substrate
have been steadily becoming more and more stringent.
This paper introduces a new multi-layer PKG substrate that has been developed to meet these market trends,and has better
features than the conventional build-up substrate. This new multi layer PKG substrate has no core material and is a so-called
coreless structure composed of only high-density build-up layers. This substrate is produced with our original manufacturing
process and has the following features: 1) Light weight (70% reduction),Thin-thickness (less than half),and High density 2)
High reliability 3) Good productivity 4) Green material.

We coated copper substrate with tin-zinc lead-free solder (Sn-9Zn and Sn-8Zn-3Bi),and then we performed the following
corrosion tests: the salt mist test,the gas corrosion test,and the weathering test. Following the tests,we visually inspected
specimen surfaces and cross-sections to determine the causes of corrosion and the extent of the corrosion to the base
substrate.
By the surface condition of the Sn-Zn solder following the various tests,it was found that corrosive substances in the
environment (such as sulfur and chlorine) reacted with the Zn in the solder to form corrosive products on the surface of the
solder. After 18 months of the weathering test,cross-sectional analysis revealed that the Sn-Zn solder had been oxidized to a
depth of 10um. However,the copper substrate underneath showed no evidence of corrosion. On the other hand,conventional
Sn-Pb eutectic solder was oxidized to a depth of 20um,and the copper substrate also showed corrosion. We hypothesize that
the corrosion of Zn in the Sn-Zn solder yielded a sacrificial corrosion effect by forming an intermetallic compound layer
(Sn-Zn layer) between the base substrate and the solder. As a result,Sn-Zn solders exhibited corrosion resistance far superior
to that of conventional Sn-Pb eutectic solder.

Much work has been done involving the introduction of RoHS and WEEE Directives across the European Union and the
world. Although the use of Pb is limited in new products and equipment,older Pb-containing materials can continue to be
used for repair of existing systems. As time progresses,these older Pb-containing materials will need to be repaired using Pbfree
components and solders. This paper addresses the concerns of repair centers,which must rework these boards using Pbfree
components and materials.

The use of lead-free (LF) solders as a replacement for traditional tin-lead (SnPb) solders in military and high reliability
applications has a number of technical challenges unique to the industry. The need for a metallurgically stable solder joint
under harsh environmental conditions,high stress and shear loading,and long term storage presents a set of requirements that
are significantly different from most commercial applications. It is well documented that processing conditions during
soldering can significantly affect the microstructure and reliability of the joint. Due to the low volume and long life cycle of
military and aerospace electronic assemblies,repair of components is widely employed. While methods for repairing
assemblies using SnPb solders are well established,limited data is available for re -work and repair of LF solder processing,
especially when the resulting joint is a combination of SnPb and LF solders. In this study the influence of repair processing
conditions on the microstructure of LF solders was investigated. Processing parameters such as soldering conditions and
solder composition were used to simulate manufacturing operations. Temperature cycling of components soldered to printed
circuit boards between -55°C and +125°C with SnPb,LF,and mixtures of SnPb and LF solders was performed. Analyses of
the phases present,chemical composition and microstructure of the solder joints before and after temperature cycling were
conducted using optical and electron microscopy to correlate processing conditions to the resulting microstructure. Shear
testing of surface mounted capacitors prior to and after temperature cycling demonstrated a significant drop in shear strength
after temperature cycling. Implications of processing conditions on the reliability and long term stability of the solder joints
will be discussed.