To meet the complex design requirements of the electronics industry,there is an increased need for large size high
I/O BGA packages. The size of these large BGA packages (up to 50 mm2 and 1157+ I/O) creates additional
manufacturability and reliability challenges. To ensure the success of these packages in manufacturing,the EMS
companies are providing manufacturability and reliability assessment services.
The influence of package size,substrate type,die thickness,Solder Mask Defined (SMD) vs. Non Solder Mask
Defined (NSMD) BGA pads,and board thickness on the board level reliability results are investigated. The
empirical test results from the Accelerated Thermal Cycle (ATC) are used to build the Finite Element Analysis
(FEA) model which allows an accurate projection of the board level reliability of similar BGA packages in various
designs. Cross Section,SEM,EDX,and Dye Penetration techniques are adopted to study the failure modes of solder
joints induced by the destructive thermal stress tests.
This study has demonstrated that board level reliability assessment conducted at the early stages of product
development is a valuable resource and can be used to ensure proper choice of components and enhance product
manufacturability.

Electronic package size reduction and demand for increased functions within less board space make a challenge for
the PCB designer to find smaller footprint components that will out perform larger sized components. The signal
density of electronic products has pushed the need for higher i/o count Ball Grid Array’s (BGAs) with smaller pitch
to be used for the transfer of signals in multi-layered PCB’s. These high pin count BGAs require excellent design for
manufacture rules along with very tight process controls to deliver a robust finished product to the marketplace.
This paper describes a PCB Test Vehicle that was used to test both the Design For Manufacture (DFM) guidelines
and the Process Controls implemented. This co-development project was to validate the design,assembly,and
process control parameters associated with using high pin count BGAS. Launching a new product using this
technology requires a joint effort to ensure “First Time Right “release and deliver the best time to market with a
robust assembly process.
The project was developed to test all aspects of the assembly process from double sided reflow process,single sided
reflow with cure process,selective wave solder process to standard wave solder processes. The goal was to
determine if there was a preferred process flow for using this new technology and if it could handle different
processes without any direct effect on functionality or yield.
Data was collected on component warpage,various temperature exposures,and their effects on the quality of the
solder joint. Visual inspection,Scanning Electron Microscope (SEM),Backscatter Atomic Number Image Contrast
(BSD) and Energy Dispersive X- Ray Analysis (EDX). Multiple EDX spectra were examined and the images were
recorded for the project.

Solderability testing is carried out at the IC (Integrated Circuit) manufacturer’s end to evaluate the quality of the IC
package terminals in terms of solder wetting ability. Current industrial standard procedures for solderability
testing—such as MIL-STD-883E and EIA/JESD22-B102-C—cover testing procedures for peripheral leaded
package types only. With the electronics industry’s recent moves towards lead-less packages and Pb-free soldering
processes,solderability issues of package terminals have become even more prominent,and universally accepted
procedures and standards of solderability testing for BGA (Ball Grid Array) packages even more urgent.
This paper describes process methodologies and their qualifications for solder joint strength and solderability tests
for BGA packages at PCB (Printed Circuit Board) level. These methodologies focus especially on BGA package
types with eutectic solder ball input/output terminals—e.g.,PBGA,Micro-BGA,FBGA,CSP,etc. Criteria taken
into account when developing the respective test methodologies included that they be practical and could be carried
out using standard SMT (Surface Mount Technology) processes and equipment. This paper concludes with
recommendations for 2 particular methodologies that proved to be the two most effective and reliable methods of
solderability testing of BGA packages on PCB board level.

With the increasing demands of complex functions in a single chipset or microprocessor,the development of large
size high I/O Flip Chip BGA (FCBGA) package becomes very important in recent years. In general,the component
suppliers will study the package level reliability data before they release the new components into market. To ensure
the quality and reliability of the products in the market,it is essential to study the board level reliability data instead.
In tradition,Accelerated Thermal Cycles (ATC) test is a widely accepted reliability test method in the electronic
industry. However,the ATC test is expensive and time consuming. It is necessary to adopt an efficient test method to
evaluate the board level reliability data for a new package design. This paper adopts the bend test technique
associated with the strain gauge measurement to learn the board level reliability data of a new designed package
under mechanical stress. Shock and vibration tests are performed to understand the product reliability under
shipping and handling environment. The shadow Moiré technique is used to study the component warpage under
different temperature points in the reflow process.
This paper presents an efficient model to study the board level reliability data for a new designed package. The
model can be used as a quick pre-qualification test and reduce the time to market of a new designed package. Some
of the tests specially designed to investigate the durability of the test component are also addressed.

In the present study,a simplified analysis methodology is used to evaluate thermal fatigue damage of solder joints of
a leadless ceramic chip carrier (LCCC) or a leadless chip capacitor/resistor (LCC/LCR). During temperature
cycling,only the solder joints experience elastic-plastic deformation while the rest of the assembly components,
such as the package case and printed wiring board,are assumed only to be elastically deformed. In the analysis,the
equilibrium of displacements of electronic package assembly is used to calculate the solder strain during temperature
cycling. This solder strain is then iterated according to the stress-strain behavior of solder until the solder strain is
consistent with the effective elastic modulus used in the analysis.
A thermal fatigue life prediction model,evolved from an empirically derived formula with some modifications,is
established. The analytical results,previously obtained from an experimentally validated fatigue life prediction
model and finite element analysis (FEA),combined with the derived solder strain are used to calibrate the proposed
model. In addition,the predicted lives calculated from the calibrated model match test results of 20-,28-,and 68-pin
LCCC packages,provided by JPL/NASA. Since this calibrated model is remarkably simple compared to the
evaluation with FEA,it is therefore recommended that this model serve as an effective tool for making a preliminary
determination of the solder joint integrity of LCCC/LCC/LCR during temperature cycling.

The energy consumed during the reflow assembly of printed wiring board assemblies is expected to be environmentally
significant within the solder product life-cycle. Wide differences in the melting temperatures of lead and lead-free solders
alternatives suggests that there may be large and important tradeoffs associated with the selection of solder and its ultimate
impact on the environment. Preliminary results of testing,conducted as part of an overall life-cycle assessment of lead and
lead free solders,are presented in this paper and then compared to previously conducted studies. Life-cycle impacts
associated the test data are also presented.
Testing results indicate that energy consumption can vary by as much as 40 percent across alternative solders,with the
National Electronics Manufacturing Initiative (NEMI) recommended Sn/Ag/Cu alloy consuming eight percent more energy
than eutectic Sn/Pb,and the Sn/Ag/Bi alloy consuming as much as 32 percent less energy. Although absolute energy
consumption values during this test were higher than other studies,relative energy differences between solder types strongly
agreed with those of previous studies. Finally,the environmental impacts associated with the energy consumed during reflow
assembly were demonstrated to be significant when compared energy use in upstream life-cycle processes.

Circuit pack assembly involves the use of numerous materials and processes of environmental concern,including
electronic components and associated assembly operations. It is necessary to be able to evaluate these in a robust,
consistent manner to provide a basis for comparison and to guide product design and project investment decisions.
Companies worldwide are seeking to include sustainability in their business and operating plans as a basis for
environmental evaluation,but are struggling to move beyond vague,subjective measures. The Sustainability Target
Method (STM) provides a practical sustainability target for individual businesses and products based on
environmental impact and market value. This paper applies the STM to evaluate selected types of circuit pack
assemblies utilized in state-of-the-art telecommunications switching equipment. The analysis includes both the
product supply line and assembly processes. The results demonstrate the product elements and processes that cause
the most environmental impact and,from a sustainability perspective,the product advancements that are occurring
due to evolving telecommunications technology and the economic value it provides.

Much of the environmental emphasis is currently on elimination of undesirable elements and compounds such as
lead or halogens. The unintended consequences are huge in terms of diversion of resources (at a time of great strain
in the electronics industry),increased energy usage,processing and performance challenges and the creation of new
questionable waste streams.
Long-term the solution for the electronics industry will be takeback and reuse or recycling. There are already models
for this in automobiles and packaging in Europe,and many of the lessons learned can be applied to our industry.
This paper outlines the necessary steps needed to establish a recycling infrastructure and the challenges we face as
an industry over the next ten years.

This paper will focus on Dr. Taguchi’s Robust Engineering methodology,measurement methods and experimental
results for the optimization of a lead free SMT process for use in an Automotive Electronics application. The key
strategy is to find process parameters that make the process insensitive to noise factors. Traditional optimization
approaches focus on maximizing the response variable while the Robust approach focuses on consistent results
regardless of variation in noise factors.
The Robust method was utilized in the development of a lead free process for manufacturing an Automotive SMT
product. Major factors that can create variation in a lead free process were identified,including lead free solder paste
brand,paste print speed,oven reflow temperatures and times,and reflow environment. Several noise factors were
studied including volume of solder paste,location of components on the board,and lead frame plating materials,
namely tin and palladium/nickel/gold. A series of measurements were made on the lead free product that assessed
the strength and reliability of lead free solder joints,measurements such as visual scoring,cross-section,surface
insulation resistance,and pull strength. Using the Robust experimental design,these measurements were optimized
to create high quality and reliable lead free SMT solder joints that were the most insensitive to the noise. In essence,
quality was increased by using variable measurements rather than by counting attributes (good/bad). Overall,a gain
of 2.1 dB was realized. In Robust terms,this equates to reducing variation in the lead free process by ~22%. This
study also revealed which of the processing factors were most significant in controlling the lead free process. The
results of this study and the use of Robust Engineering methodology provide a means for developing a full range of
lead free technology,components and products used on Automotive Electronics.

With the US military now committed to the phasing
out of lead-containing solders via the Joint Group on
Pollution Prevention (JG-PP) the electronics industry
has moved beyond debate about whether to make this
move and onto the question of how to implement the
change to lead-free solders as quickly as possible
without increasing cost or reducing reliability. The
Japanese industry began this change several years
ago and already has a vast amount of experience in
practical lead-free soldering and the resolution of the
technical issues that were inevitably encountered.
Although,because of the impact of legislative
pressure lead-free solders were initially used mainly
in consumer electronics the commitment of the
industry to environmental protection has meant that
these solders are now being introduced across a wide
spectrum of electronics. In this paper some of the
technical challenges encountered in the
implementation of lead-free solder will be discussed
and the solutions reported. The conclusion is that the
electronics industry can meet the challenges
presented by the phas ing out of lead-free solders in
much the same way as it deal with earlier challenges
such as the phasing out of CFC cleaning solvents and
the introduction of surface mount technology.