Copper migration such as conductive anodic filaments (CAF) has become a serious problem for printed wiring
boards (PWBs). As the relation between CAF and matrix resin properties is not clear,the relation has been
investigated by estimating the influence of resin properties and resin/glass fiber interfaces on the CAF property.
New evaluation techniques have been applied to resin materials affecting CAF. The dissolution of copper ions
surface into the matrix resin in contact was measured electrochemically. The amount of copper absorbed on the resin
powder surface was measured by atomic absorption spectroscopy. It was found that some CAF-restraining resin
systems will either prevent copper dissolution or capture the dissolved copper ions. A new resin system modified for
such purpose showed better CAF resistance than the conventional resin system.
In addition,the interface adhesion strength was estimated by using an acoustic emission (AE) method. It was found
that a new system called Filler Interface Control System (here-in-after: FICS) will afford good interface adhesion
and resultant good CAF resistance.

BGAs are usually solder-reflowed on substrates,which are frequently made of a different material than that of the
BGAs,which results in a TCE Mismatch between the components. If such an assembly includes a large size BGA,
and is exposed to thermal or power cycling,the solder joints undergo a high level of stress,which could ultimately
lead to the premature failure of the assembly.
This has been one of the challenging problems in the electronics industry. Several designs have been proposed in the
past to counteract the unfavorable effect of such conditions. For example,the author,together with other coinventors,
had addressed this problem,starting in 1982. They invented what was called CCMD,Chip Carrier
Mounting Device,later called Cherian Columns or Solder Columns or Solder Quick. These solutions were useful at
their time,and were covered by a number of patents. Other attempts have been made by additional inventors. Some
were more successful than others.
An additional current problem however,is the fact that many of the components are being miniaturized. The center
distances between contact pads are getting smaller and smaller,and the old inventions can no longer keep up with
such miniaturization. For example,BGAs have center distances down to 0.020 inch (approx. 0.5 mm) and when
Chip Scale Packaging is considered,the center distances are even smaller. The Solder Columns were originally
designed and built to work with 0.050 inch (approx. 1.25 mm) center distances. They cannot be simply scaled down
to size.
For this reason,the author has re-visited this problem and came up with improved solder columns. In this paper,
some of the findings will be shared along with a few of the suggestions and solutions that resulted from this research
and studies.

The IPC-PCQR2 (Process Capability,Quality and Relative Reliability) program has developed a library of process
capability panel designs,and a database that details the manufacturing capability,quality,and reliability of printed
circuit board suppliers. The database includes comprehensive reports of each supplier's capabilities,reports that
allow for a direct statistical comparison of suppliers,and reports that provide a concise summary of the industry's
performance at large. This paper presents background information on the PCQR2 program,and the latest industry
performance data collected by the PCQR2 program.

The information age has arrived. A growing percentage of the Earth’s population now has access to pagers,cellular
phones,computers,personal digital assistants (PDA’s),and a host of other electronic devices. We can now instantly
communicate around the globe with a device that fits into the palm of the hand. To meet these demands,packaging
houses are shrinking the pitch of their interconnects to assist in reducing overall package size. Some of these
developments are made possible through advances in HDI (High Density Interconnect) flexible circuit technology -
its key attributes being packaging adaptability,circuit density,and configurability on less real estate. Almost every
flexible packaging company has a road map to reduce the pitch of the conductor traces below 50mm. Many flexible
circuit designs with areas of 50mm pitch are already in production. Designs are on the drawing board to shrink the
pitch to 30 mm.
The demand for increased packaging density has intensified pressure on process,production,and quality personnel
to ensure product can be produced in a timely manner at acceptable yields. Electrical testing can detect opens and
shorts in the package,but cannot detect the near opens or near shorts that cause early field failures. Visual inspection
by humans is virtually impossible,not to mention unreliable given the reduced circuit pitch configurations. These
traditional inspection methods do not produce process feedback to improve the manufacturing process. Automated
Optical Inspection (AOI) is now a necessary production tool to produce quality product at acceptable yields.
However,standard AOI technology cannot accurately inspect the fine pitches being manufactured in the HDI
flexible circuit arena. This paper will discuss a method for implementing AOI into HDI-flex manufacturing and how
it serves as an enabling technology by providing reliable,consistent 100% inspection. Furthermore,this paper will
illustrate how proper implementation and integration of AOI can provide real-time process feedback and the
resultant yield increases that accrue.

There are a number of organic,inorganic,and hybrid inorganic waveguide materials that are currently being used for
a wide variety of optical interconnect applications. Depending upon the approach,waveguide formation is
performed using a combination of lithographic and/or reactive ion etch (RIE) techniques. Often the processes
involved with waveguide formation require unique processing conditions,hazardous process chemicals,and
specialized pieces of capital equipment. In addition,many of the materials have been optimized for silicon substrates
but are not compatible with printed wire board (PWB) substrates and processes.
We have developed compositions and processes suitable for the creation of optical,planar waveguides on both
silicon and PWB substrates. Based on silicate technology,these compositions use lithographic techniques to define
waveguides,including aqueous,alkaline development. The resulting planar waveguides take advantage of the glasslike
nature of silicate chemistry wedded with the simplicity of standard lithographic processes. Attenuation at typical
wavelengths has been found to compete well with the non-silicate-based technologies available today. Single-mode
(SM) and multi-mode (MM) waveguides with losses ranging from 0.5 dB/cm @ 1550nm,0.15 dB/cm @1320nm,
and <0.1 @ 850nm are feasible. Composition,process and physical properties such as optical,thermal and
mechanical properties will be discussed.

Multiple soldering assembly steps are essentially
standard for PWBs based on current technologies and
needs. A variety of tests are currently in use to
evaluate the performance of finished PWBs,and
indirectly,the materials and material performance of
the substrate laminate materials used. These tests,as
exemplified by the “6 X 288°C Thermal Shock Test”
currently in vogue,tend to focus on via and
interconnect reliability. These tests are also often
combined with life-cycle testing,such as traditional
thermal cycling or IST testing,to gauge in-use
reliability performance,again focusing on PWB
reliability. Substrate materials have an inherent
ability to pass or fail these various tests but with a
high dependence on PWB design and the production
processes used to produce the PWB. The maximum
ability of a substrate to perform to a certain level can
be viewed as the performance entitlement of that
substrate. A PWB fabricated from a given substrate
material can meet the performance entitlement of that
material but never exceed it. The work presented in
this paper is primarily an attempt to develop new
analytical test methods to determine the performance
entitlement of various laminate substrate materials.
Conclusions presented focus primarily on the test
methods under investigation and only on the
observed differences where the results seem to point
to obvious conclusions that are consistent with prior
art and experience.

A new oxide chemistry has been developed which
solves many of the annoying properties of the
currently available alternate oxides. The process is
simple to operate,even simpler to maintain,requires
less chemistry,manages to be easier on the
innerlayers,is highly conducive to waste treatment,
and is significantly lower in cost. And although the
cost of the chemistry is significantly lower,the
biggest savings will be in the reduction of the waste
treatment costs. However,the rumors that use of the
chemistry can cure,or even prevent,cancer must be
vigorously denied,pending further testing.

Solder is used in polyimide-based flexible circuits for interconnect applications. But it cannot be used with polyester
and epoxy based substrates because of the low temperature tolerance of these substrates. Conductive adhesives offer
the best alternative for this application because they can be processed at lower temperature. Other advantages
provided by conductive adhesives are lead-free,no flux/no cleaning,and fine pitch application. There are two types
of conductive adhesives in the market. Type I is the traditional conductive adhesive used predominately with
expensive components on ceramic substrates. These high cost components are terminated with noble metals such as
Au,Pd or Pt that offer no corrosion concern under 85°C/85%RH. To reduce the cost of components,eutectic solder
or high tin solder is used as termination metal. Unfortunately,these non-noble metals are subject to corrosion that
causes unstable electrical performance when the type I conductive adhesives are used as the interconnect. This
shortcoming triggered the development of type II "solder alternative" conductive adhesives that exhibit stable
contact resistance with Sn/Pb-terminated components under various environments including 85°C/85%RH. This
case study focuses on the development of an advanced type II conductive adhesive and its use as an interconnect on
polyester-based flexible circuits. Adhesives are applied by high-speed stencil printing followed by low temperature
cure for a short time. Stable electrical performance and adhesion performance with Sn/Pb terminated components
are demonstrated under several environmental conditions. The effects of application and processing conditions on
adhesive performance are typically overlooked while making adhesive selection. This study includes the results of
the electrical and mechanical performances under various curing profiles and various stages of stencil printing.

Adhesiveless copper on polyimide substrates are used extensively for high density,flexible circuit applications. A
typical construction includes the polyimide substrate,a thin vacuum deposited metal tiecoat,a copper seedcoat,and
an electrodeposited copper layer. One or both sides of the polyimide may be metallized,and very thin copper can be
provided in order to facilitate formation of fine-line features. Since metal layers are direct deposited,not laminated,
the copper profile and bond treatment typically associated with copper foils are not present between metal and
dielectric. Adhesion between metallization and dielectric is achieved by performing plasma pretreatment prior to
metallization,and by the selection of a suitable tiecoat metal. Tiecoat metal is especially important to minimize
adhesion losses associated with circuit processing and subsequent environmental exposures. In this work,
characteristics of copper on polyimide substrates with nickel-chromium tiecoat are investigated. Adhesion,before
and after exposure to elevated temperature,pressure cooker conditions,and gold plating,is determined as a function
of tiecoat thickness. Additional characteristics,including etching performance and a practical example of using the
material to manufacture a high-density circuit,are discussed.

Failure analyses of the leadfree and SnPb solder joints of high-density packages such as the PBGA (plastic ball grid
array) and the CCGA (ceramic column grid array) soldered on SnCu HASL (hot-air solder leveling) ENIG
(electroless nickel-immersion gold) or NiAu,and OSP (organic solderability preservative) Enteek PCBs (printed
circuit boards) are presented. Emphasis is placed on determining the failure locations,failure mode,and IMC
(intermetallic compound) of these high-density packages’ solder joints after they have been through 7500 cycles of
temperature cycling. The present results will be compared with those obtained from temperature cycling and finite
element analysis.