Yield and defect levels in the manufacturing of high-complexity and high-reliability Printed Circuit Board
Assemblies (PCBAs) are extremely sensitive to variations in the process,component quality and workmanship. Any
deviation from expected targets needs to be investigated,not only after the identification of the manufacturing issue,
but also proactively before the issue becomes more pronounced. Traditional control tools such as yield tracking
and/or Statistical Process Control (SPC) capture deviations in the overall defect levels but they have no knowledge
what specific types of defects to monitor. In addition,the discontinuous nature of production build schedules and
fluctuating product volumes in the high-mix and low-volume electronics manufacturing domains can render SPC
ineffective. This research proposes a new methodology that interprets and analyzes defect and yield data to detect
“maverick lots”. These defect clusters are delineated from large volumes of production data in a high-complexity
PCBA facility that contains accurate information mixed indistinguishably with “noisy” data. For this approach,
historical information from prior analysis is used to distinguish deviations and trends from the current data. This
procedure is generic in nature and could be simultaneously executed automatically at several appraisal points on the
manufacturing line. This methodology has been used effectively in the Endicott Interconnect In-Circuit Test process
and has identified shifts in our Complex Assembly processes that may have gone undetected using other techniques.

Numerous studies and anecdotal data suggest that most SMT assembly lines are not optimized. This situation is true
whether one looks at the individual processes,such as stencil printing or placement,or the entire SMT assembly line
as a whole. This lack of optimization causes significant losses in profits. Most managers and process engineers are
aware of this general situation,but feel overwhelmed with deciding how to address the concern.
In light of this need,we have developed an Excel® based software program. This program asks the user a series of
questions. The answers to the questions are then analyzed by the program. The output is an assessment of the users
SMT Process and a recommended approach to developing a continuous improvement plan. The assessment ranks
the user in categories that relate to specific processes,such as reflow or printing and suggests areas of improvement.
More importantly,the assessment determines the competitiveness of the assembler’s entire SMT process and offers
constructive criticism. SMT “systems” topics such as statistical process control (SPC),designed experiments (DOE),
and design for manufacturability (DFM) are included in the assessment.
The entire assessment process takes most assemblers less than one hour and the results can be invaluable in
developing an effective continuous improvement process.
The software will be given free to interested readers. Contact the authors for copies of the software and an
instruction guide.

Wave soldering fluxes are currently used in hand soldering operations as a matter of course and with little
regard for flux deposition amounts. This use has led to the investigation of fluxes used in hand soldering
applications and the effect on long term reliability of manufactured assemblies. The work presented here
explores the reliability impact that fully,partially and entrapped wave flux residues from hand soldering repair
operations can have on electronic assemblies. Standard IPC Surface Insulation Resistance (SIR) testing and
testing with a different environmental condition of 40°C at 88% R.H. were performed to determine reliability.
During hand soldering operations,liquid flux can become entrapped under nearby components or flooded onto
areas of the assembly that may not be heated. The results of SIR testing show that if fluxes are used properly in
controlled amounts there is no associated reliability impact. However,some fluxes if applied in excessive
amounts or entrapped were shown to cause reliability failures. In particular these problems occurred with noclean
tacky soldering flux (TSF),rosin activated (RA) and no-clean,low solids fluxes. During hand soldering
operations flux deposition should be carefully controlled to reduce the potential for entrapped and excessive
flux residues that can lead to long term reliability problems.

Surface Mount Rework systems have evolved into sophisticated thermal processing tools with the ability to
accurately mimic original reflow oven profiles at a localized rework site. Features such as automated profile
generation allow the user to quickly define workable profiles for a wide variety of applications. However,many of
today’s applications demand more carefully crafted profiles than can be achieved using traditional methods.
Sensitive components such as optical devices,connectors,and certain package types,to name a few,have specific
requirements and limitations that go far beyond the typical solder joint time-temperature profile. Elevated
temperatures of lead free processes further amplify thermal management issues.
Rules Based Thermal Profiling allows automated profile generation with a combination of parameters that that are
set to meet each situation. Multiple criteria may be specified and prioritized to yield the most reliable process for
reworking sensitive components and assemblies.

SMT rework machines are vital tools to many production engineers. They can be used to correct process errors and
repair test failures. They can also be used to service and upgrade products returned from the field.
Rework machines come in many forms – from the basic hot air type to complex laser and infrared heating units.
Whichever form they take,they have a common task - to deliver focused heat for the removal,replacement or
repositioning of SMT electronic components.
This paper discusses the need to control these systems on a daily basis. It addresses current methods and will offer
some alternatives and improvements. Finally,it suggests a statistical regime that will ensure machines are operating
in a controlled manner.

Current circuit board designs,particularly those in telecommunications,are so densely populated that they do not
provide enough clearance between SMT components and through-hole components to allow assemblers to use
traditional soldering methods. Clearances of less than 0.5mm (0.020”) are typical in these designs. To provide
assemblers with robust,repeatable selective soldering processes,equipment manufacturers have been challenged not
only to miniaturize the traditional flux-preheat-wave process,but also to add sophisticated positioning,motion
control,and optical recognition systems. This paper describes the many selective soldering challenges encountered
by assemblers,the current state of the art in automated selective soldering,and the future of this technology.

Wave and reflow soldering are well known,successfully proven mass soldering techniques. They offer the ability to
solder printed circuit boards in high volumes quickly with low defect levels,producing high quality solder joints.
Other available soldering techniques (e.g.,vapor phase,laser and hand soldering) are limited in terms of throughput.
Continued trends toward miniaturization in printed circuit design and assembly are resulting in increasingly more
surface mounted devices on the board,finer pitches and overall less space. Between the SMD components,however,
there remain,on many assemblies,a small number of through-hole components that either don’t have SMD
counterparts or are unique,or are there for other reasons. Selective soldering machines are typically used in the
production environment to solder these components.
This paper concerns the selective soldering process,wherein a robot is employed to bring circuit boards in contact
with the solder in order to individually solder through-hole components to the board. Other selective soldering
processes employ soldering tools mounted beneath a conveyor system. Except for the tools (e.g.,fluxer and solder
nozzle) that are different from the wave soldering process,these processes have nothing truly new to offer that may
benefit board designs. A robot system implementing a soldering process enables the use of new techniques that offer
the ability to solder different parts of boards,or even boards themselves,to another. This paper seeks to address the
possibilities of this process for mass soldering and tries to identify the limits of the process and its parameters.

The use of laser technology has found increasing applications in the electronics assembly industry. This non-contact
heating technique is ideal for components that require careful handling which otherwise might be damaged due to
the joining methods currently used. The main focus of this research effort is to evaluate the use of lasers as an
alternative energy source to attach flexible circuits to rigid boards. A designed set of experiments is performed to
optimize the different identified factors. The variables include different base materials for the flexible circuit,flux
chemistry,solder alloy,and operating parameters on the laser soldering machine. Various low-cost base materials
are identified and their performance is evaluated by performing strength tests on the joints to evaluate their
robustness. Further analysis included X-ray inspection for voids and cross-sectioning.

In both the server and portable electronic markets,monotonic mechanical overstress has become a primary issue in
manufacturing and field usage. Appropriate test methods,including four point bending,can be used for pro-active
design optimization.
The mechanical margin of safety in electronic assemblies has been decreasing over time. This is in part due to larger
component body sizes,increased PWB thickness,and reduced component stand-off. Identification of mechanical
fragility is important to assess the failure risk during manufacturing and field usage.
This paper will describe a four point bending test method utilized to examine the critical variables that influence
component failure levels. Testing was done on multiple package types mounted to two different PWB thicknesses.
Many components showed significant resilience to bend loading. Failures at different strain rates showed a
correlation between strain rate and monotonic failure point.

To meet the complex design requirements of the electronics industry,there is an increased need for large size high
I/O BGA packages. The size of these large BGA packages (up to 50 mm2 and 1157+ I/O) creates additional
manufacturability and reliability challenges. To ensure the success of these packages in manufacturing,the EMS
companies are providing manufacturability and reliability assessment services.
The influence of package size,substrate type,die thickness,Solder Mask Defined (SMD) vs. Non Solder Mask
Defined (NSMD) BGA pads,and board thickness on the board level reliability results are investigated. The
empirical test results from the Accelerated Thermal Cycle (ATC) are used to build the Finite Element Analysis
(FEA) model which allows an accurate projection of the board level reliability of similar BGA packages in various
designs. Cross Section,SEM,EDX,and Dye Penetration techniques are adopted to study the failure modes of solder
joints induced by the destructive thermal stress tests.
This study has demonstrated that board level reliability assessment conducted at the early stages of product
development is a valuable resource and can be used to ensure proper choice of components and enhance product
manufacturability.