In recent years,technological advances in electronics manufacturing have allowed high volume manufacturers to
significantly improve process control and documentation. Manufacturers have accelerated the use of solder paste
and component vision systems,x-ray analysis,and in-circuit feedback systems to drive manufacturing defects to low
parts per million (ppm) levels. One of the latest opportunities for delivering improved process yields is in the control
and documentation of the reflow environment.
This paper investigates the use of comprehensive reflow profiling systems to control the reflow temperatures within
the reflow environment and document the temperature range for specific locations on a printed circuit assembly. The
analysis will also evaluate the capability of the automated reflow monitoring system to accurately measure thermal
regions within the oven over a wide variety of profiles,board designs,materials,and production volume. Finally,
this analysis investigates the impact of temperature control on solder joint quality using several different solders and
substrate materials.

The drive for electronic devices to become lightweight,more portable,and posses increased functionality has driven
electronic components to smaller and smaller sizes. This decease in size does not only apply to active devices such
as chip scale packages (CSPs) and area array devices,but also to discrete components,such as capacitors and
resistors. This has lead to an increase in the use of 0402 and 0201 sized components. These components represent a
significant decrease in size from other discrete components. The major challenge with these components is typically
issues with processing. One of the most common defects associated with these small components is tombstoning. A
variety of solutions have been proposed for reducing or eliminating tombstoning. To date these have mostly been
changes in design and/or processing. Implementing these changes after production has begun can be costly and time
consuming. Also,even if some of these changes are implemented other process factors can contribute to an increase
in tombstoning. This paper presents a materials based solution to the tombstoning issue. This solution widens the
process window with respect to tombstoning and has been used to reduce the occurrence of tombstones in
production. Causes of tombstoning,case studies,and the mechanism behind how the material reduces tombstoning
will be presented.

Solder beading and tombstoning are observed increasingly with chip components as their size decreases. This is
even more crucial in today’s packaging,due to the high ratio of passive components in comparison to active
components. The increasing number of passive components affects the Defects Per Million Opportunities (DPMO),
which inturn affects the overall yield of the assembly line. Hence,it is vital to understand the various causes within
the assembly process,which influence the occurrence of these defects. This paper will discuss the results of a
process characterization study to understand the effects of solder paste,stencil thickness,board support,reflow
profile and the component size on the formation of solder beads and tombstones. A Resolution-V DOE analysis was
performed to determine the effect of these factors on the defect occurrence. The response variable for the study was
% defects,the ratio of number of defect occurrences to the total number of available defect opportunities.

The trend in electronics packaging towards product miniaturization,has forced the industry to use fine pitch area
array packages instead of fine pitch leaded packages. These area array packages enable higher production yields and
are less prone to handling damages,thereby enhancing the system throughput. Incorporating these packages into the
assembly and also achieving the required process robustness,requires a thorough understanding of the process
variables and the ability to control them.
As indicated in various research publications,the solder paste print process is very critical to the assembly of these
packages. This process contributes to 60-70% of the assembly defects. Hence,the Center for Electronics
Manufacturing and Assembly at RIT undertook an investigative study,using Taguchi techniques,to identify the
critical factors and improve the robustness of the stencil printing process,for fine pitch area array packages.
Taguchi’s robust design technique is a viable analysis tool for evaluating complex processes that involve a multitude
of variables. Prior process knowledge is required to understand the effect of various parameters and the results of
Taguchi experiment.
The Taguchi analysis utilizes signal to noise ratio calculations to reveal the effect of process variables such as print
pressure,print stroke and separation speed,on paste volume variability and % transfer. Details of this study and the
analysis are presented in this paper. Significant conclusions about board finish,aperture size and shape and stencil
manufacturing technology were inferred and are discussed in the paper. Moreover,this case study can serve as a
quick reference to perform Taguchi analyses for similar process studies.

Quantitative solder paste performance or use testing enables material formulators to focus on and maximize key
material traits such as wettability and printability. These same material test methods and tools allow SMT engineers
to fine tune reflow profiles,stencil aperture design and specific print parameters. A fourth generation multi-purpose
test vehicle design has been developed and is discussed in detail. Specific quantitative tests for printability,abandon
time,wettability,slump,solder beading and balling,tombstoning,pin testability and X-ray voiding have been
incorporated into one test board. Methods to extract quantitative data and “score” a material for objective
comparisons are discussed.

Today’s SMT assemblies are being driven toward SMD’s with higher lead densities as well as smaller packages.
This places additional performance requirements on the printing process. The stencil printing process has a major
influence on SMT assembly yields. It is important to consider stencil design,aperture design,and stencil printing
performance when selecting a stencil. This paper will focus on stencil printing performance and,specifically,how to
choose the correct stencil to increase SMT assembly yields.
Stencil print performance is evaluated over a range of stencil technologies including: Electroform,Laser-cut,Lasercut
with Electropolish and Nickel plate,and Precision Chemically - milled stencils. A total of 23 different stencils
were evaluated in the study. These stencils are made using the exact same Gerber file. Stencil printer set-up,solder
paste,and solder volume measurement set-up is identical for the stencils. Print studies were performed in an
independent test laboratory. Solder volume is measured for 8 different device types,including the following: 0201,
uBGA 20 mil pitch,0402,CBGA 40 mil pitch,16,20,25 mil pitch QFP’s and uBGA 31mil pitch. Stencil print
performance will be evaluated by measuring solder paste volume,solder paste volume dispersion,misprints
(bridging or insufficients) and positional accuracy of the stencil apertures. Physical properties of each stencil such as
aperture size,aperture wall smoothness and aperture cross section are measured. This information will be used to
predict SMT assembly yields for the array device types listed above. The yield data is then used to predict rework
cost related to the different types of stencils included in the study. Paste relax and recovery tests using three solder
paste types and five stencil types is reported. In this test dwell time between prints is varied from 15 minutes to 90
minutes.

In the complex electronics industry,supply chain costs can have a major impact on a company’s profitability. Like
the industrial supply chain,where costs are estimated to account for as much as 8% of a company’s operating
income,the electronics supply chain has many points that can affect the bottom line.
Assembly manufacturers,suppliers and contract manufacturers can positively impact their bottom lines by
optimizing their supply chains. Opportunities are greatest when companies focus on the big picture and make
improvements that benefit the entire operation.
One example of a supply chain improvement that can pay big returns for electronics component assemblers is
something they might not have considered: a returnable packaging system.
Returnable packaging systems contribute much more than durable,ESD-protective containers for shipping
components. They deliver cost-savings and efficiency at multiple points on the supply chain. The improvements
can add up to much greater financial benefits than most companies realize,including:
• Cuts in the Cost of Goods Sold
• Limits on Selling,General and Administrative Expenses
• Reduced Capital Costs
This paper presents a new way of looking at returnable packaging: how it can optimize the supply chain,where it
improves the bottom line,and how companies can achieve maximum return on their investment.

Solder paste for use in wafer bumping applications is becoming an extremely viable technology. Yields from solder
paste printing applications are approaching that of typical bumping technologies. The lower cost associated with
printing technology is driving the flip chip industry to adopt this low-cost method of bumping. This investigation
examines the variables of wafer bumping using solder paste printing techniques. A multiple factor designed
experiment was used to optimize printing parameters for solder paste deposition. Factors examined included: types
of solder paste,powder distribution,stencil type,print speed,and print pressure. The responses measured included
the volume of solder paste deposited and variability of the solder paste depositions.

The relentless trend for smaller,lighter,cheaper consumer products continues to fuel the demand for new,smaller,
efficient electronic packages. In recent years wafer level packaging concepts have emerged,providing multiple
design wins in terms of form factor and production costs. Performing all processing at the wafer level prior to dicing
provides obvious cost advantages whilst the WLP footprint offers a 1:1 component to package ratio.
Solder bumping usually represents the final stage in the WLP assembly process prior to dicing. Standard solder
paste print and reflow techniques can be utilised but the resultant bumps invariably fall below specifications due to
process limitations. More commonly,dedicated equipment sets that place pre-formed solder spheres onto the wafer
are used.
This paper details work undertaken to combine the benefits of standard stencil printer technology with that of solid
solder sphere placement to enable the development of a low cost,flexible system for the bumping of wafer level
packages. In addition,an alternative print & reflow technique based on an extrusion concept was also investigated.
The two techniques are compared for the bumping of a 0.5 mm pitch WL-CSP product.
The work undertaken forms part of the European funded IST-2000-30006 "Blue Whale" programme which is
concerned with developing next generation wafer level packaging for handheld applications in a LAN environment.
Project partners include Philips CFT,Shellcase,Technical University of Berlin,Technical University of Delft and
DEK Printing Machines Ltd.

A technique that enhances the release of solder paste from stencils during the print process has been developed. The
technique is based on applying variable high frequency and low amplitude vibrations to the stencil during the
stencil/substrate separation sequence. The effects of the technique are demonstrated in the context of bumping
wafers. It is shown that the enhanced print technique produces wafers with fewer defects,greater bump heights and
better height uniformity than when conventional stencil printing is used without the enhancement technique.