HDPUG's Reliability Testing and Data Analysis of High-Density Packages Lead-Free Solder Joints

Temperature cycling test and statistical analysis of various high-density packages on PCBs with SnCu HASL,NiAu,
and OSP finishes are investigated in this study. Emphasis is placed on the determination of the life distribution and
reliability of the lead-free solder joints of these high-density package assemblies while they are subjected to
temperature conditions. A data acquisition system,failure criterion,and data extraction method will be presented
and examined. The life test data is best fitted to the Weibull distribution. Also,the sample mean,population mean,
sample characteristic life,true characteristic life,sample Weibull slope,and true Weibull slope for some of the highdensity
packages are provided and discussed. Furthermore,the relationship between the reliability and the
confidence for a life distribution is established. Finally,the confidences for comparing the quality (mean life) of
lead-free solder joints of high-density packages are determined.

Author(s)
John Lau,Nick Hoo
Resource Type
Technical Paper
Event
IPC APEX 2003

HDPUG's Design for Lead-Free Solder Joint Reliability of High-Density Packages

The lead-free solder-joint reliability of the high-density packages,256-pin PBGA (plastic ball grid array),388-pin
PBGA,and 1657-pin CCGA (ceramic column grid array),on PCB (printed circuit board) subjected to temperature
cycling is investigated. Emphasis is placed on the determination of the creep responses (e.g.,stress,strain,and strain
energy density) of the lead-free solder joints of these packages. The lead-free solder is assumed to obey the
Garofalo-Arrhenius creep constitutive law. The results presented herein should be useful for a better understanding
of the thermal-mechanical behaviors of the lead-free solder joints in these high-density package assemblies.

Author(s)
John Lau
Resource Type
Technical Paper
Event
IPC APEX 2003

HDPUG's Lead-Free Design,Materials and Process of High Density Packages

The High Density Packaging Users Group (HDPUG) has conducted a substantial study of solder joint reliability of
high-density packages using lead-free solder. The design,material,and assembly process aspects of the project are
addressed in this paper. The details on the design are addressed from the aspect of the considerations taken in the
design process,and not just the design details. The components studied include many SMT (surface mount
technology) package types,various lead and PCB (printed circuit board) finishes and paste-in-hole assembly. The
assembly process addresses lead-free assembly process,inspection and analysis of these boards and packages. Leadfree
transition issues are also discussed.

Author(s)
Joe Smetana,Rob Horsley,John Lau,Ken Snowdon,Dongkai Shangguan,Jerry Gleason,Irv Memis,Dave Love,Walter Dauksher,Bob Sullivan
Resource Type
Technical Paper
Event
IPC APEX 2003

Analytical Imaging Techniques for Hard Die Coated Assemblies

With the advent of hard die coated microelectronic assemblies; the ability to perform visual inspections for quality control
and failure analysis has been seriously hindered. Analysts have had to utilize X-ray inspection,cross sections,and chemical
decapsulation to discover what defects are hidden under the hard die coat. X-ray analysis cannot see aluminum bond wires or
areas of delamination on and under the electronic components and substrates. Cross sections and chemical decapsulation
techniques are destructive and will alter the physical condition and electrical operation of the assembly.
Using an acoustic microscope,recent analytical work has been able to identify individual components involved in high
voltage electrical overstress events,evaluate silver epoxy die attach dispense patterns,inspect epoxy bleed out for shorting
between components,detect wire sweep in aluminum bond wires,and locate fused copper traces within the top three layers of
a printed wire board assembly.
This presentation will discuss the imaging requirements through hard die coated assemblies,the physical process variations
and failure mechanisms which may be present,and the acoustic microscopy techniques which can be used to see through the
hard die coat and successfully document them.

Author(s)
Kristopher D. Staller
Resource Type
Technical Paper
Event
IPC APEX 2003

New Insights in Underfill Flow and Flip Chip Reliability

During the last years Flip Chip Technology has been widely accepted as a means for maximum miniaturization of
microelectronic assemblies. As an example the use of Flip Chips in advanced products as cellular phones,GPS
devices and in medical applications for pacemakers can be named.
These Flip Chip assemblies have proven to yield at least comparable reliability as standard SMT packages with a
reduced package or product volume resp.. To achieve this reliability it is necessary to carefully select the materials
and the process parameters.
At Fraunhofer IZM previous investigations on processibility and reliability have been updated using state of the art
Flip Chip Underfillers. Motivation for the investigations is,that for industrial use it is necessary to have defined
encapsulation process parameters that guarantee a robust process without internal flaws. As these flaws often result
from non-optimized material parameters an easy way to detect critical material combinations or assembly geometry
was investigated. The investigations performed correlate calculated flow rates to results from in situ flow
measurements. Here the direct flow visualization using video equipment (e.g. flow front fingering) was combined
with acousto-microscopic visualization of material inhomogeneities (e.g. comet-like filler agglomerations).
Furthermore the influence of different substrate base materials,solder mask types and geometries on five different
underfill materials is considered and related to material flow and filler agglomerations as detected and visualized by
acoustic microscopy. For further material evaluation concerning the reliability of the selected material systems
accelerated aging tests are performed. During process setup and accelerated ageing tests the use of Acoustic
Microscopy allowed the precise detection of material imperfections as variations in filler distribution or voiding. As
these internal flaws are critical to Flip Chip reliability it is crucial to avoid such effects.
Derived from these investigations a material ranking of the underfillers used was done and material systems suited
for the assembly of reliable Flip Chip packages have been identified.

Author(s)
K.-F. Becker,N. Kilic,T. Braun,M. Koch,V. Bader,R. Aschenbrenner,H. Reichl
Resource Type
Technical Paper
Event
IPC APEX 2003

MSD Control in a High Reliability Production Environment

The Information and Electronic Warfare Systems
business of BAE SYSTEMS Information and
Electronic Systems Integration,Inc. (“BAE
SYSTEMS IEWS”),a subsidiary of BAE SYSTEMS
North America,is involved in the manufacture of a
wide range of military products for the government.
One of the manufacturing focus factories within the
IEWS group deals strictly with the production of
Circuit Card Assemblies (CCA). The CCA focus
factory performs the hardware build for programs
internal to the company and supports a contract
manufacturing organization that seeks work from
outside the company as well. To that end,the CCA
Focus factory is best characterized as a low volume,
high mix manufacturing environment. Given the type
of business in which the CCA focus factory is
engaged,areas of improvement are continually being
identified. One such area pertains to the management
of Moisture Sensitive Devices (MSD). With the help
of Cogiscan Inc. of Quebec,Canada,a solution to
this industry wide problem of effectively managing
MSDs has been addressed.

Author(s)
J. Cambrils,M. Hickey,D. Tibbets
Resource Type
Technical Paper
Event
IPC APEX 2003

Lead Free Reflow Process Control

All areas of manufacturing worldwide are impacted
by the lead free initiative; none more than the reflow
process. The higher melt temperatures and soak
duration of leadless solder formulas require a change
in the way reflow management is handled. Time
above liquidous,grain structure,and board exit
temperatures all require tight definition within a
shrinking process window. Also,until all components
and boards are 100% lead-free,we will be working in
mixed territory. Lead-free solders combined with
components and/or boards that have lead bearing
finishes will definitely impact the reflow formula in
contradictory ways. Since every board configuration
is different and there are many lead free solder
formulas to choose from,this means every assembly
could be completely unique. Because of this,there is
no magical panacea; no standard simple profile that
will fit all assemblies and all leadless solder
formulas. You will have to basically “know your
stuff” and only good use of statistical process control
(SPC) will allow you to do this. Hopefully,the
information in this presentation will help you
understand the why and wherefore of SPC in lead
free SMT reflow; and introduce you to
methodologies,new tools and software that will
make a tight SPC reflow program relatively fast and
simple to both understand and implement.

Author(s)
Karl Fischbeck,Fred Dimock
Resource Type
Technical Paper
Event
IPC APEX 2003

Advances in Shop Floor Equipment Communication Standards for Final Assembly and Packaging

The Final assembly and packaging area experiences similar integration issues as the Printed Wiring Board –
PWB manufacturing industry. Communications between production equipment is based on different standards
and many vendors have released their own proprietary specifications. This situation entails considerable
integration costs.
Most of the equipment suppliers in final assembly and packaging have implemented information systems using
proprietary specifications. Some of the Original Electronics Manufactures (OEM) and Electronics
Manufacturing Service companies (EMS) request SECS/GEM interfaces. However,SECS/GEM is not always
suitable,especially in those cases when the equipment has moderate functionality. The final assembly and
packaging area is calling for an explicit and scalable solution.
The development of an IPC-2546 section dedicated to final assembly and packaging will improve the
information flow integration. Leading suppliers drive,by consensus,the development of this sectional standard.
In addition,control issues (related to IPC 2556) were kept in mind from the very beginning of discussions.
CAMX(+) standards are developed based on the PWB manufacturing needs. In case of final assembly and
packaging the environment and conceptual design differs from PWB. New levels of abstraction are needed. A
representative case for these differences is the transportation system using pallets (containers). In addition the
route of the product is not typically straightforward,but branching is a common situation creating extra needs
for the controls.
A test environment was built up in order to develop,test and illustrate these standards. The environment uses a
pallet-based transportation system for interconnecting manual workstations and robotized cells.
The tests indicate the applicability of CAMX standards in final assembly and packaging area. When a common
language is used,the Plug & Assemble ideology is achieved providing lower costs. Production equipment users
are able to select the best-in-class machines and integrate them into multi-vendor systems. Finally,the use of
same messaging format provides a homogenous environment from equipment through the enterprise to B2B.

Author(s)
Reijo Tuokko,Niko Siltala,Jose L. Martinez Lastra
Resource Type
Technical Paper
Event
IPC APEX 2003

PCB Equipment Communication Standards Today and Tomorrow

All manufacturers in the printed circuit board (PCB) industry have experienced lack of reliability,maintenance,and
performance problems with their machines. These challenges decrease manufacturing productivity and increase
costs. Addressing these manufacturing challenges requires the right process information to be available to the
engineering team. Currently,managers and process engineers either have insufficient or no data to measure the
impact of these issues in order to make improvements. It is essential for the industry to use the adopted equipment
communication standards that provide the basic framework to gather the data necessary to dramatically improve
equipment utilization.
The industry has been using the Semiconductor Equipment Communication Standard/Generic Model for
Communications and Control of SEMI Equipment (SECS/GEM) standards that allow manufacturers to gather data
directly from the equipment. Several factories that have used SECS/GEM have published their remarkable process
improvements. Experience demonstrates that SECS/GEM is most reliable when equipment suppliers use robust
software products created by third party developers to implement the interface and provide it as a standard feature.
IPC is defining new communication standards for retrieving information from the equipment based on Extensible
Markup Language (XML),a common and popular communication language. The new standards promise facilitated
access to process information in order to increase equipment efficiency and reduce costs.
Equipment suppliers are already required to support the SECS/GEM standard for certain customers. Today,machine
suppliers are on the verge of also supporting the IPC XML standards as manufacturers adopt the new standards.
Suppliers and factories should avoid developing non-standard protocols to implement equipment communication
interfaces and instead use the existing standards as a baseline and implement special messages to fulfill any
additional requirements.

Author(s)
Brian L. Rubow
Resource Type
Technical Paper
Event
IPC APEX 2003