The behavior of BGA solder joints under dynamic loads has become more significant in recent years. This work explored test
methodologies for solder joint failure evaluation under dynamic loads. The objectives of this study were
• To evaluate the behavior of solder joints under a variety of strain rates as seen during both 4 point bend testing and
mechanical shock
• To try to quantify the shock levels present at solder joint failure to support ongoing solder joint reliability modeling
efforts
A test coupon and fixture developed for the four point bend test setup is reviewed. Testing was performed under different
strain rates and the results showed clearly that the solder joint failure is strongly strain rate dependent under mechanical
bending load on boards. This implies that the practice of low strain rate (quasi-static) test with dynamic amplification factor
for solder joint failures,such as the four point bend test,is not sufficient for dynamic prediction due to over-estimation of the
joint strength at low strain rate range. The finite element analysis revealed that the strain rate dependent material properties of
the solder play the key role of solder joint failure threshold.
Comparison of strain rates between the four point bend test and a more traditional mechanical shock test were made on a
desktop motherboard. These tests showed that the strain rate is much higher during the mechanical shock test than that seen
during the bend testing. A variable mass shock test and an incremental shock test procedure were developed to evaluate BGA
solder joint shock failures. In-situ solder joint continuity was monitored during the shock events. The results of these tests
give a good estimate of motherboard BGA solder joint robustness.
In addition,a shock test fixture and a test vehicle were developed similar to those used in the four point bend test. By using
the incremental shock test procedure outlined above,the acceleration level (G-level) at solder joint failure was obtained. This
information was input to the finite element dynamic analysis,the overall behavior of the test coupon during shock was
simulated and the solder joint failure force obtained. Failure analysis of the shocked boards revealed that PCB pad/FR4
disbond was the dominant failure mode for the tested eutectic solder joints. In addition,fracture at IMC between pad and
solder on the package side was observed.
In summary,a set of test and modeling methodology for solder joint reliability evaluation under dynamic load was developed
and validated and some recommendations are made as to the applicability of these test methods.

Industry cost control pressures and technology drivers demand more powerful 3D AOI machines for control of solder paste
printing. Here is an inside look at the factors potential purchasers of these systems should take into consideration.

The electronic industry trend of smaller component packages and tighter spacing has put greater demands on manufacturing
for process control and product verification. Defects must be caught earlier in the process to provide feedback to the process.
Large quantities of manual rework on components that can barely be seen or handled put too much strain on rework
operators. Manual inspection as a means of process control has become less effective by these factors causing fatigue,
missing defects,and reduced thru-put. In-circuit test as a means of product verification also has issues because it requires
space on the printed circuit board for test pads. Automated Optical Inspection (AOI) is an increasing popular method to
address process control and product verification. Faster processors with higher density memory devices have enabled image
capture and processing to become a viable alternative. This paper will detail the methodology used to select and evaluate AOI
systems as an alternative process control and product verification tool.

Conductive adhesives (CAs) have been an important problem-solving class of assembly materials for decades,but primarily
as die attaches products,ever since they replaced metallurgical systems. Renewed and intensified interest in lead-free (L-F)
electronic assembly has moved CAs back into the spotlight. Although lead-free solders,both new and very old,have been
studied for several years,they are a partial solution at best. One may conclude that: (1) lead-free alloys do work,(2) there is
no drop-in replacement,and (3) their higher processing temperatures are detrimental.
The expected increase in soldering temperatures is cause for concern over potential damage to laminates,packages and some
semiconductors. New alloys will also require modifications to some soldering equipment. High temperature L-F processing
could bring significant and costly “collateral damage”. BGAs could require pre-bakes,PWBs may degrade and optoelectronic
components could fail or suffer reduced lifetimes. The next -generation sub-micron CPUs,with evolving low k dielectric
layers,may not tolerate excessive soldering temperatures. These problems may be "fixed",but not truly solved. Cost-adding
work-around strategies include higher performance laminates,upgraded molding compounds and in-process cooling,but
considerable time and money will be needed to re-engineer,re-test and re-qualify.
Polymer Solders (Conductive Adhesives) have provided a good alternative for temperature-limited assembly for decades.
These well-tested joining materials process like solder on the same equipment. Fluxing or cleaning is never required. And
they run at more than 100 degrees lower than solder. Both reflow and batch ovens can be set at 110oC to 150oC to quickly
harden these polymer systems. Adhesives are used to assemble SMTs to a variety of systems including medical devices,
memory modules,and computers. Chances are that LEDs in your business phone and ink jet printer are assembled with
conductive adhesives. Perhaps the flip chips driving your flat panel display are adhesively bonded.
This paper will compare Polymer Solders to L-F alloys to show limitations and advantages for the technology. There are
important restrictions,especially lower mechanical strength revealed in the drop test. But adhesives research has been
energized after years of simple incremental improvements and fresh new approaches will be summarized that include
intrinsically conductive polymers (ICP) and Nanomaterials.

Quantifying SMT adhesive dispensing performance has typically been attribute analysis via a microscope. Individual
adhesive deposits were inspected for strings or tails,extra dots,missing dots and dot diameter. These attributes were typically
measured with an eyepiece reticule and a light microscope. This tedious and subjective method has been replaced by a highly
quantitative,extremely quick automated method using the vision engine of a real time X-ray. The details of this method are
discussed as well as practical applications for glue benchmarking and dispense parameter fine-tuning. The output of this
method includes dot diameter,spherocity and area. Adhesive deposit consistency of both dispensing and printing are
compared using this novel measurement method.

Higher I/O Ball Grid Arrays (BGAs) are high speed,high pin count,and high performance array packages. These BGAs are
also more complex in structure than “standard” BGAs and are generally targeted toward network and server class products.
Higher I/O BGAs follow an industry trend identified on multiple industry roadmaps and vendor data sheets. Today,
component manufacturers are introducing higher I/O BGAs into the market.
Along with the speed and performance benefits,these higher I/O BGAs also incorporate additional manufacturing and
reliability challenges. For example,these larger sized BGAs are considered more susceptible to component warping and large
temperature deltas during reflow because of their large size. This paper will discuss overcoming these challenges in regards
to one new type of high I/O BGA: a 2577 I/O,1.0mm ball pitch,52.5 x 52.5mm body size,PTFE carrier,Flip Chip BGA
(FCBGA).
The main objective of this study is to describe and discuss the component characterization,test vehicle design,assembly,
rework,and accelerated temperature cycling testing that were done with the 2577 I/O Hyper BGATM. Component warpage,
overcoming large temperature deltas during reflow,reworking techniques,and analysis of the accelerated temperature
cycling will be discussed.
Another objective of this study is to discuss process considerations for assembling and reworking the 2577 I/O Hyper
BGA.™

With the function of today’s electronic devices become more and more complicate,the high I/O flip chip ball grid array
package (FCBGA) is used more popularly in recent years. The FCBGA package is always subjected to thermal loading when
in use. For accelerating the reliability access,the thermal effects is often checked by using bend tests instead of the time
consuming thermal cycling tests. However,most of the bend tests are performed at room temperature. But in reality,the load
is applied at the state of elevated temperature. The study will investigate the thermal reliability issue by bend test with
consideration of temperature effects.
In the study,the reliability of FCBGA is explored by a four-point bend test executed at different controlled temperature. The
test vehicle is put in a heated chamber and the resulting daisy chain resistance and strains are monitored to check its failure.
Both the monotonic and cyclic tests are used. However,during the monotonic bend test,the failure mode is found to be the
delamination of the heat spreader instead of the solder balls cracking. It is then conducted with room temperature only by
checking the failure mode of heat spreader delamination. The cyclic bend test was done with various temperature loading
conditions. Based on the results from the monotonic test,it is then reduced the loading so that the heat spreader failure won’t
occur prior to the solder ball fatigue failure is observed. The strain gages are mounted near the component corner to get the
strains of the test board when under bending. A data logger records the daisy chain resistance simultaneously during the test.
The component failure is detected with a self-written program by judging when the failure resistance of the daisy chain is
large than 20% of its initial resistance.
The test results at various temperature showed that the component life cycle is reduced with the increase of the temperature
during the cyclic bend test when under a fixed maximum deflection setting. If tested at room temperature by varying the
maximum deflection,the component life cycle is also reduced with the increase of the maximum deflection in the cyclic bend
test. Through the fitted curve of all these test data,it is then possible to get relating equations among the variables of
temperature,deflection,and life cycle. An extra test is conducted to verify these deduced equations with an error of six
percent approximately. The methodology can be used to predict the component life cycle at elevated temperatures based on
the test results at room temperature.

In recent years,Wafer Level Chip Scale Packages (WLCSP) are used not only in the hand held devices but also in high-end
networking and telecommunication products. Due to their small footprint and the bare die structure,long-term board level
reliability is a concern particularly in high-end applications. Using underfill material in these WLCSP components may
present a possible solution for reliability improvement. Non-reworkable underfill material is generally used in low cost,
small,hand-held devices for better reliability. However,in high end products with expensive boards,the option to rework
WLCSP components need to be considered. It is therefore important that an underfill material with both good “reworkability”
and “reliability” be identified. This paper examines the board level reliability improvement of six (four nonreworkable and
two reworkable) underfill materials on 0.5 mm pitch WLCSP component. The possible correlation of different material
properties to reworkability and reliability of the underfill material will be discussed. An underfill material with good
reworkability may sacrifice the reliability at the same time. The findings have confirmed the fact that proper selection of the
underfill material for small footprint WLCSP component can improve the reworkability and reliability in high end products.

The trends of increased functionality and reduced size of portable wireless products,such as handsets and PDAs,are
demanding increased routing densities for printed circuit boards. The handheld wireless product market place demands
products that are small,thin,low-cost and lightweight and improved user interfaces. In addition,the convergence of handheld
wireless phones with palmtop computers and Internet appliances is accelerating the need for functional circuits designed with
smallest,low-cost technology.
Historically,the industry has met this challenge through high density interconnect technology and increased silicon
integration and component miniaturization. Microvia high density interconnect (HDI) also known as build up technology,is
one method for constructing circuit boards with high routing density demands.1
For HDI board,vias can be formed using unreinforced dielectric such as Resin Coated Foil (RCF) using processing
techniques such as laser drilling or photoimaging. The vias are then metallized using electroless copper / electrolytic plating.
The advantage of the HDI construction is the ability to create smaller vias (6 mils) and via pad sizes. This enables higher
routing density,lower metal count,reduced board area and increased functionality as compared to conventional boards.
Past board technologies used at Kyocera- Wireless Corporation used single stack of microvias on the outer layers. (Layer 1-2
and Layer 7-8). Current phone technology boards have stacked microvias,Layer 1-2 and layer 2-3. Additionally,these vias
are filled with electroplated copper while the single stack vias were plated,but not filled.
The paper presents the evaluation conducted to ensure the stability of these vias thru the Reflow process. This study was
done as a part of a phone product qualification build.

The objectives of the present study are to design,fabricate,and test various configurations of micro-vias over military
thermal environment,and then evaluate the impacts of micro-via design/manufacturing process variables on the thermal
fatigue damage of the micro-vias. The selected parameters are solder mask on printed wiring board,micro-via pitch,and
micro-via size,with each having either two or four levels of variation. A test vehicle (TV),into which the daisy-chained
micro-vias combined with all these selected parameters are incorporated,is first designed and fabricated,and then subjected
to temperature cycling from -55ºC to 125ºC with continuous monitoring of micro-via integrity. A total of 26 TVs are used in
the present study and the micro-via failure is defined as an electrical discontinuity.
Based on monitored results,a destructive physical analysis (DPA) is conducted to further isolate the failure locations and
determine the failure mechanisms of the micro-vias. Test and DPA results indicate that: 1) the smaller the micro-via sizes,the
higher the occurrence of manufacturing defects; 2) the micro-vias,having electrical continuities before the test,can survive
1000 temperature cycles; and 3) there is no influence or inclusive observation of the micro-via pitch variation on the microvia
fatigue damage. In addition,a thermo-mechanical analysis with nonlinear finite element computer code applied in a 100
µm (or 0.004 in.) diameter micro-via is performed to illustrate this micro-via integrity when subjected to thermal cycling.
Further evaluation of the impacts of the micro-via pitch and diameter variations on the micro-via thermal fatigue damage by
finite element analysis is recommended.