A novel technology for embedding discrete capacitors in a mezzanine layer of an HDI PWB was developed and
implemented by Motorola in partnership with its PWB supply chain. The technology is based on the use of a
ceramic -filled positive type photo-dielectric to form discrete,embedded capacitors with capacitance densities
ranging from 10 to 30 pF/mm2. Capacitor test vehicles were designed,fabricated at multiple sites,tested,and used to
characterize the electrical performance and reliability of embedded mezzanine capacitor structures.
In this paper,the novel ceramic -filled dielectric capacitor fabrication process is outlined. Electrical tests are
reviewed,indicating a relative dielectric constant greater than 20,a loss tangent of less than 4%,and breakdown
voltages in excess of 100V for 11µm thick dielectrics. For reliability testing,minor variation in capacitance is
observable following multiple reflow cycles,liquid-to-liquid thermal shock,or air-to-air thermal cycling. A larger
shift in capacitance is observed following temperature-humidity storage,but the change is shown to be reversible.
Finally,two case studies are presented for RF modules using this embedded capacitor technology. In each case,area
usage is reduced while maintaining or reducing the overall module cost.

Design and processing of ceramic resistors and capacitors fired onto copper foil and embedded into FR4 circuit
boards are presented and discussed. Evolution of design guidelines and processing for embedded ceramics is
presented and discussed. Design tolerances are slightly larger for embedded ceramics because of the extra firing at
high temperatures experienced by the copper foil on which the resistors and capacitors are printed. Scaling of the
resistor and capacitor terminations must be done during print-and – etch operations.
Ceramic bodies are weak in tension and very strong in compression,so the most important processing precaution is
to minimize tension experienced by the resistors during high temperature firing and lamination. Somewhat reduced
lamination pressures is helpful. Limiting the size of resistors and capacitors is also helpful for capacitors. Size of
resistors is usually not a problem except for very small resistors below 10 mils in size Designs for these applications
include specially formulated pastes with thermal expansion behavior higher than is optimum for ceramic resistors
and capacitors on alumina substrates. In addition,protection of the ceramic components from the stress of the
lamination steps is desirable for the resistors. This is provided by encapsulating the resistors in a filled encapsulant
that reduces the expansion of the epoxy resin,and scatters the laser energy applied during resistor trimming,so that
the PWB itself is not harmed while being laser trimmed. Performance after processing appears excellent by usual
environmental tests; and board flexure encountered in bend tests does not appear to be a problem. To date,five mil
resistors appear too small to be screen printed with good CV and reliability. Ten mil and larger resistors are
adequately stable.

Various requirements have developed for printed wiring boards regarding the minimum spacing between features.
Creepage distances per UL-60950 call out 1.2mm for voltages up to 50v,and call out 1.4mm for voltages up to
100v,for products classified under pollution degree2 material group IIIa. IEC-664 has an altitude factor that needs
to be added for any product that is designed to go over 2000m altitude (for 3000m product there is an additional 14
percent). Tyco has established rules,which do not allow spacing on a product to go below certain minimums,
depending upon the class of product. The UL-1012 sets spacing limits for power supplies. Telcordia GR-78,Section
13.1.5,specifies minimum 10 megohms (10E+10 ohms) after 1,000 hours at 85 ?C,85% RH,and 100 VDC bias as
their minimum standard for electrochemical migration resistance testing for an expected 25 year minimum product
life requirement.
For many years Sun Microsystems has required a minimum 0.035 inches from drilled hole wall edge to drilled hole
wall edge for adjacent component holes,and minimum 0.025 inches from drilled hole wall edge to drilled hole wall
edge for adjacent through-hole vias,for certain standard voltage requirements. These standards for electrochemical
migration resistance between internal features or the printed wiring board,also known as resistance to conductive
anodic filament growth or "CAF" resistance,were based upon earlier AT&T data and actual experience by Sun
Microsystems with products in the field. Today more and more boards are being designed with relatively high I/O
PBGA packages,and associated with these devices are fairly dense arrangements of through-hole vias. The
increases in trace routing density are also driving higher via density. New connectors are being developed which
have higher pin density and/or need to carry higher voltages. As a result of these trends,there is strong interest in
more accurately evaluating the corresponding electrochemical migration or CAF reliability risk for a variety of
component and via plated-through hole-to-hole spacing.
The following paper documents some of the difficulties faced in developing a temperature/humidity/bias test and
data analysis methodology for comparing the electrochemical migration or CAF resistance of various standard and
alternate printed wiring board (PWB or PCB Fab) la minate materials. These findings should be of interest to those
evaluating material,design,and process effects on electrochemical migration resistance. Please note that this
electrochemical migration paper focuses on CAF formation,not surface dendritic growth.

This paper describes a process for plating of interconnects for advanced electronic modules. In contrast to traditional
chemical mediation of plating processes,this process is electrically mediated and does not rely on difficult to control
brighteners/levelers. The methodology for selection of the electric mediation parameters is based on considerations
of mass transfer and microprofiles/macroprofiles related to current distribution. This paper builds on earlier work by
incorporating plating cell/tank design issues including air agitation,eductor agitation,eductor orientation,back and
forth panel movement and knife-edge panel movement. Data for plating industry test panels containing microvias
and PTHs of approximately 4:1,10:1,and 20:1 aspect ratios are presented.

Many printed circuit board manufacturers report that the measured value of the differential impedance is a few ohms greater than the calculated value when the substrate is FR4. There may be several reasons for these differences:
???accuracy of the software used
???accurate knowledge of the track cross-section
???variation of the dielectric constant of the substrate
The software used by the authors,1 agrees,where possible,with good accurate theoretical impedance equations,particularly when the track thickness is zero. In addition,the new software referred to in Section 3,gives values of impedance which are within 25x10-2% of the values calculated by the software of Reference 1. Thus it is concluded that the calculated impedances are accurate.

The ideal outer layer has a uniform circuit height throughout the board. This is a challenge to produce with pattern
plating,because the plated metal height depends on the current density,which varies across the board,based on the
size and proximity of features being plated. The resulting board typically has areas where the plating height is higher
than desired (overplated),and can be particularly acute in areas of fine lines and spaces. In these areas,if the plating
overlaps the top of the resist,then the resist is difficult to strip cleanly,and this can be the limiting factor in whether
a fine line board can be made in production.
Clean stripping from overplated lines is an area of active research in our laboratories,and we would like to report
the factors in resist design and processing that affect it,and recommendations for driving to finer lines and spaces in
production.

The demand for small packaging for portable electronic equipment and reduced chip form factor with higher interconnect fan-out,is driving printed circuit substrate technology rapidly forward. The demand is for smaller,thinner,lighter,more reliable and,of course,cheaper devices. Just consider the paradigm provided by the cellular phone,the laptop or the PDA in less than a decade. At the interconnect level this means ultra thin high layer count PCBs,densely populated on both sides,maximizing surface mount 'real-estate' and that requires high density interconnectivity. Reducing PCB line and space widths is certainly a proven method for increasing circuit density,but further reductions will demand significant process control improvements to prevent yield losses from driving production costs up. Enhanced interconnectivity is a second important driver. Today's 'state-of-the-art' boards call for a rapid growth in this. This demand,for escalated pad density,is being met by a variety of techniques with every increasing hard to remember acronyms,most of which require high density interconnect structures. A better target for major leaps in connectivity improvement comes from a reduction in the size of via holes and their associated lands,which per se immediately creates more routing tracks between pads. The HDI PCB in 1997 averaged ~ 485 I/O's per square inch,in 2001 it was closer to 1,800. As device form factors shrink and I/O density mushrooms,the size of vias must fall and their number increase. Expressed in another way,the typical '97 PCB via count of 20,000 has increased by more than a magnitude to closer to 250,000. Currently there are several entry routes for the manufacture of PCBs with laser drilled micro via interconnect features:
1 "Half-Etch" route
2 "Conformal Mask" route
3 Thin Foils + Oxide Conversion route
We will describe the key features and disadvantages of each of the current production techniques.

The development of digital printing systems for printed circuit board legends (a.k.a. nomenclature,indent or letter
screening) is a major technological leap. Legend marking on printed circuit boards (PCB) is presently being
accomplished with screen-printing. This method of marking legends on PCB’s provides a permanent,high contrast
mark,however,this technology is costly in terms of material and labor. Screen-printing is a mature technology that
is well understood in the industry and well supported by screen ink providers. A successful digital printing solution
for this application will retain the benefits of permanent,high contrast marks and offer advantages of demand
printing including efficient runs of small production batches.
An emerging technology in PCB legend marking is drop-on-demand (DOD) ink jet. DOD ink jet offers the
flexibility of digital printing while also providing high contrast,high resolution marks with the required performance
properties. The primary advantage of DOD ink jet printing enables PCB’s to be printed directly from image files
eliminating the need for screens and greatly reducing the setup time required between batches. As the PCB industry
is challenged to reduce costs and improve turnaround times,drop-on-demand ink jet shows promise in reshaping the
printing process.

This paper presents a comparison of several resin systems on different support reinforcements including on
Thermount®1 (or NWA),E-Glass (or E),and NE-Glass2 (SITM) (or NE). The resin systems compared in this paper
include D53001 (Halogen-Free,High Tg or HFHT),N4000-13 (high-speed/low-loss or HSLL),and N4000-6 (high
Tg FR4 or HTFR). It is proposed that the HFHT resin can be used for high-signal speed applications,chip-test
boards,and in some cases,lead-free solder PCB processes. The parameters compared herein include thermal,
mechanical,dielectric (i.e.,stripline tests),flame -retardant character,and cure profile characteristics. This study
gives the chip-test board,backplane,and wireless base-station designer valuable information concerning the
functionality of these resin systems with different support reinforcements.

The physical placement of embedded singulated capacitors in relation to one another and to other board structures could have an impact on the measured capacitance of individual capacitors. For board designs requiring tight tolerance of an embedded singulated capacitor,knowledge of the influence of board design on the measured capacitance would be of interest. A designed experiment tested the effect of 3 factors: distance between capacitors (capacitator spacing),the presence of an additional ground plane in the board,and having a common ground for the adjacent capacitors. Test design,board construction,and resulting capacitance measurement data will be presented. The results showed that all 3 main factors and 1 interaction term were significant. The significant interaction was between capacitor spacing and common ground.