In recent years,Wafer Level Chip Scale Packages (WLCSP) are used not only in the hand held devices but also in high-end
networking and telecommunication products. Due to their small footprint and the bare die structure,long-term board level
reliability is a concern particularly in high-end applications. Using underfill material in these WLCSP components may
present a possible solution for reliability improvement. Non-reworkable underfill material is generally used in low cost,
small,hand-held devices for better reliability. However,in high end products with expensive boards,the option to rework
WLCSP components need to be considered. It is therefore important that an underfill material with both good “reworkability”
and “reliability” be identified. This paper examines the board level reliability improvement of six (four nonreworkable and
two reworkable) underfill materials on 0.5 mm pitch WLCSP component. The possible correlation of different material
properties to reworkability and reliability of the underfill material will be discussed. An underfill material with good
reworkability may sacrifice the reliability at the same time. The findings have confirmed the fact that proper selection of the
underfill material for small footprint WLCSP component can improve the reworkability and reliability in high end products.

The trends of increased functionality and reduced size of portable wireless products,such as handsets and PDAs,are
demanding increased routing densities for printed circuit boards. The handheld wireless product market place demands
products that are small,thin,low-cost and lightweight and improved user interfaces. In addition,the convergence of handheld
wireless phones with palmtop computers and Internet appliances is accelerating the need for functional circuits designed with
smallest,low-cost technology.
Historically,the industry has met this challenge through high density interconnect technology and increased silicon
integration and component miniaturization. Microvia high density interconnect (HDI) also known as build up technology,is
one method for constructing circuit boards with high routing density demands.1
For HDI board,vias can be formed using unreinforced dielectric such as Resin Coated Foil (RCF) using processing
techniques such as laser drilling or photoimaging. The vias are then metallized using electroless copper / electrolytic plating.
The advantage of the HDI construction is the ability to create smaller vias (6 mils) and via pad sizes. This enables higher
routing density,lower metal count,reduced board area and increased functionality as compared to conventional boards.
Past board technologies used at Kyocera- Wireless Corporation used single stack of microvias on the outer layers. (Layer 1-2
and Layer 7-8). Current phone technology boards have stacked microvias,Layer 1-2 and layer 2-3. Additionally,these vias
are filled with electroplated copper while the single stack vias were plated,but not filled.
The paper presents the evaluation conducted to ensure the stability of these vias thru the Reflow process. This study was
done as a part of a phone product qualification build.

The objectives of the present study are to design,fabricate,and test various configurations of micro-vias over military
thermal environment,and then evaluate the impacts of micro-via design/manufacturing process variables on the thermal
fatigue damage of the micro-vias. The selected parameters are solder mask on printed wiring board,micro-via pitch,and
micro-via size,with each having either two or four levels of variation. A test vehicle (TV),into which the daisy-chained
micro-vias combined with all these selected parameters are incorporated,is first designed and fabricated,and then subjected
to temperature cycling from -55ºC to 125ºC with continuous monitoring of micro-via integrity. A total of 26 TVs are used in
the present study and the micro-via failure is defined as an electrical discontinuity.
Based on monitored results,a destructive physical analysis (DPA) is conducted to further isolate the failure locations and
determine the failure mechanisms of the micro-vias. Test and DPA results indicate that: 1) the smaller the micro-via sizes,the
higher the occurrence of manufacturing defects; 2) the micro-vias,having electrical continuities before the test,can survive
1000 temperature cycles; and 3) there is no influence or inclusive observation of the micro-via pitch variation on the microvia
fatigue damage. In addition,a thermo-mechanical analysis with nonlinear finite element computer code applied in a 100
µm (or 0.004 in.) diameter micro-via is performed to illustrate this micro-via integrity when subjected to thermal cycling.
Further evaluation of the impacts of the micro-via pitch and diameter variations on the micro-via thermal fatigue damage by
finite element analysis is recommended.

In the present as in the past,printed circuit board conductors are sized using simple charts that are a function of
cross-sectional area,current level and conductor temperature rise. These charts do not distinguish between copper
weights,board thickness,and they do not take into account internal copper planes,components,or mounting
configurations. In addition,they do not provide information with respect to the vias,thermals,copper planes or
heavier copper weights.
Research into the current-carrying capacity of electrical conductors has lead to the development of a new IPC
standard to be used for sizing electrical conductors. This new standard is IPC-2152,Standard for Determining
Current Carrying Capacity in Printed Board Design. This new document will deal with conductors in the most
general of terms,that being any metallic media conducting current. This paper discusses where the existing design guidelines
originated and new information that will be incorporated into IPC-2152.

Various Ag-filled epoxies were subjected to a current carrying capability study in which current was applied to the
epoxies at temperatures of up to 170°C for 1008 hours. Test devices with Ag epoxy joint diameters ranging from
7.29 to 9.46 mils were stressed at temperatures of 100°C,150°C,and 170°C. A maximum current of 0.5 amps was
applied,resulting in equivalent current densities ranging from 1003 to 1858 A/cm2,depending on joint diameter.
Data suggests that each high temperature Ag-filled epoxy can survive current densities of up to 1245 A/cm2 when
exposed to temperatures up to 170°C for 1008 hours.
Subsequent cross sections of each epoxy show no indication of electromigration or separation of the Ag particles
after the 1008 hours. The results of this evaluation indicate that high temperature Ag-filled epoxies are capable of
surviving elevated temperatures and high current densities for extended time intervals. This gives a viable lead free
solution for many product assemblies.

Horizontal conveyorized spray processing is the most prevalent method for the production of circuit panels in the
industry today. However,as line and space requirements fall below 4 mils (100µm),the difficulties in producing
panels with high yields and tight tolerances seem to increase exponentially. In the quest for solutions to these
difficulties the seemingly age old question of whether fan or cone nozzles are best for developing and etching high
density interconnects has once again been raised. The fluid dynamics at the surface of the panel are discussed along
with the problems associated with them. The physical properties of the two different types of nozzles are compared
and test data is presented from comparison tests in developing and etching. The conclusion is reached that; while
there are advantages and disadvantages to each type of nozzle,either one is capable of producing good high density
interconnect panels with high yields and tight tolerances in a well-designed spray-processing machine. Going from
one type of nozzle to the other alone is not going to magically resolve problems encountered in producing highdensity
circuit panels.

Predicting printed circuit board (PCB) thickness has not historically been a difficult task. With lower layer count
boards you can afford for the prediction per layer to be wrong by a relatively large amount and still meet thickness
criteria. As layer counts in multilayer boards increase,the ability to predict final thickness after lamination becomes
more difficult and more important. All else equal,as the layer count increases,the error you can tolerate per layer
must be reduced.
This paper discusses a method to design a thickness prediction model for a specific board shop process. This is
accomplished by running carefully constructed experiments and assembling the results into a mathematical
prediction model. The results will show how,in one case,thickness prediction errors were reduced by more than
25%.

Customer demands concerning thermal stability of PCB base materials are increasing. Rising complexity of
printed circuit boards requires an improved quality of the dielectric in terms of cleanliness.
With this background,Multek Europe tested various High-Tg-FR-4 base materials. The tests were divided in
thermomechanical (Cu adhesion,Tg,Time to Delamination,Solder Shock Tests,Pressure Cooker Tests) and
quality investigations (Cu cladding quality,inclusions in the dielectric,HiPot test performance) of the laminate,
characterization of the prepreg (rheological) and a check of the Material Safety Data Sheet.
The paper deals with the tests and their relevance for PCB production or assembly and discusses the results
obtained with the various materials.

In order to evaluate the relative merits of halogenated and alternative flame-retardants used in PWB’s,a comparison
between several different PWB’s each having different flame-retardant packages has been made. The study examines
the leachability of each of the PWB’s,the products obtained from simulated combustion of each PWB,and factory
monitoring of a preferred halogen free PWB. For the combustion tests,incipient fires were simulated using
DIN53436 protocol and tests were carried out at 260ºC and 600ºC in an ISO/TR 9122 apparatus. Leaching studies
were performed using US EPA Method 1311 - TCLP (Toxicity Characteristic Leaching Procedure).

Combination grid-prober (CGP) testing is being
employed with increasing frequency as the density of
SMD lands on boards continues to increase. A
number of factors are at work. Grid testers,as a
stand-alone test methodology,provide a fast and
comprehensive test,but they require costly fixtures
and suffer from intermittent "false opens" when
testing very dense or fine pitch boards. Flying probe
testers,on the other hand,are exceptional in their
ability to handle density and fine pitch,but they
unfortunately suffer from long test times relative to
grids. The test time penalty is so severe,that in some
quick turn environments,fixture test is the preferred
methodology only because lead-time does not exist to
probe the boards. Since the total cost of test is lower
for flying probe than grids below quantities of about
500 boards,some board manufacturers are adding
flying probe capacity in much the same way that
multiple drill machines together provide the capacity
to meet production volume. While this solution may
be satisfactory for some,it is cause to reassess
combination grid and prober testing as a better use of
capital.